Design Verification Engineer
- Salary
- $226K - $445K
- Level
- Mid
- Work type
- Hybrid · San Francisco
Not stated in the posting: visa.
Open. First seen 7 March 2026.
About the role
About the Team:
OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.
About the Role
OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.
In this role you will:
- Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
- Define verification plans based on architecture and microarchitecture specs.
- Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
- Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
- Drive bug triage, root cause analysis, and work closely with design teams on resolution.
- Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.
You might thrive in this role if you have:
- BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.
- Proven success verifying complex IP or SoC designs in industry-standard flows
- Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).
- Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.
- Familiarity with performance modeling, formal verification, or emulation is a plus.
- Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.
To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.
About OpenAI
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.
OpenAI's standard text
We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.
For additional information, please see OpenAI’s Affirmative Action and Equal Employment Opportunity Policy Statement.
Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.
To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form. No response will be provided to inquiries unrelated to job posting compliance.
We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link.
OpenAI Global Applicant Privacy Policy
At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.
What this role asks for
Particular to this role
Verilog
Rare in OpenAI's other 299 open postings.
60% of this description is written for the role. The rest is OpenAI's standard text, folded away below.
Read against OpenAI's other open postings on this site.
The team: Hardware HIRES STEADILY
This role is one of 27 open in Hardware. 3 were posted in the last 30 days and the oldest in October: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
C++ (12 of 27), Embedded Systems (11 of 27), Rust (11 of 27), Python (10 of 27), C (9 of 27), Linux (6 of 27), Linux Kernel (4 of 27)
OTHER ROLES ON THIS TEAM
- SoC Engineer posted Oct 14
- Software Engineer, DevOps posted Oct 1
- Supply Chain Operations Program Manager, AI Infrastructure posted Sep 24
- Mechanical Engineer, Hardware Systems posted Sep 16
- Software Engineer, Manufacturing Infrastructure posted Sep 16
- Physical Design Engineer posted Sep 15
- Hardware Strategic Sourcing Manager, Optics posted Sep 11
- Hardware Systems Planning Lead (1P) posted Sep 4
- Software Engineer, AI accelerator Runtime posted Aug 24
- Systems Software Engineer, Silicon Bringup posted Aug 24
- Software Engineer, Model Runtime posted Aug 24
- Product Manufacturing Engineer - PCBA posted Aug 20
- Hardware Strategic Sourcing & Manufacturing Partnerships Manager posted Aug 19
- RTL Design Engineer – Interconnect & Network Datapath posted Jun 23
- Systems Software Engineer, Security, First Party Hardware posted Jun 8
- Manufacturing Test Engineer posted Jun 5
- Host Systems Software Engineer posted Jun 3
- Supply Chain Program Manager (SCPM) - AI Infrastructure posted May 14
- Systems Software Engineer, Management Plane posted May 7
- Networking Operating System Firmware Engineer posted May 6
- Software Engineer, GPT Infrastructure posted Apr 27
- Software Engineer, Kernel Performance & AI Tooling posted Apr 17
- Hardware / Software CoDesign Engineer - 3P posted Mar 21
- Component and Product Quality Engineer, Interconnects posted Feb 12
- ASIC Firmware Engineer, Modeling posted Feb 3
- Signal Integrity Engineer posted Jan 22
From the team and dates on OpenAI's own job board.
Salary context
21 other open postings titled Design Verification Engineer state a salary: median USD 175,000 to USD 308,500 a year.
Similar jobs
- Design Verification Engineer at Apple
Same title - Design Verification Engineer at Apple
Same title - Design Verification Engineer at Apple
Same title - Design Verification Engineer at Apple
Same title - Design Verification Engineer at Apple
Same title - Design Verification Engineer at InnoPhase IoT
Same title
Is this your posting and you want it taken down? Email info@careerholo.com.