Sr. ASIC Design Engineer (Silicon Engineering)
- Salary
- $165,000 - $270,000
- Level
- Senior
Not stated in the posting: work type, visa.
Open. First seen 1 October 2026.
About the role
SpaceX's standard text
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together.
We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable.
Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Evaluate architectural trade-offs based on features, performance requirements and system limitations
- Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
- Work closely with verification team to ensure all aspects of the design are covered and verified
- Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
- Participate in silicon bring-up and validation
BASIC QUALIFICATIONS:
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- 5+ years of experience in RTL implementation
PREFERRED SKILLS AND EXPERIENCE:
- Ability to solve complex problems including clock domain crossings and power optimization
- ASIC/SoC system integration experience
- Experience with embedded CPU subsystems
- Experience with standard bus protocols (e.g. AXI, AHB, etc.)
- Experience with high speed and low power design techniques
- Scripting skills (e.g. Python, etc.)
- Experience with EDA tools such as HDL simulators and HDL Lint tools
- Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
- Enjoys being challenged and learning new skills
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours or weekends as needed for mission critical deadlines
COMPENSATION AND BENEFITS:
Pay Range:
Level 3: $165,000.00 - $270,000.00
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.
You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees in Washington State accrue paid sick time in compliance with state and federal law. Company shuttles are offered to employees for roundtrip travel from select Seattle locations to the SpaceX Redmond office Monday to Friday.
ITAR REQUIREMENTS:
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX's standard text
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.
What this role asks for
Particular to this role
Verilog
Rare in SpaceX's other 299 open postings.
Standard for embedded / hardware roles
Embedded Systems · Python
Common in embedded / hardware postings at any company.
82% of this description is written for the role. The rest is SpaceX's standard text, folded away below.
Read against SpaceX's other open postings on this site.
The team: Silicon Engineering HIRES STEADILY
This role is one of 43 open in Silicon Engineering. 7 were posted in the last 30 days and the oldest in May: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Embedded Systems (43 of 43), Python (39 of 43), Perl (17 of 43), Verilog (16 of 43), Bash (15 of 43), FPGA (13 of 43), C++ (8 of 43)
OTHER ROLES ON THIS TEAM
- Sr. ASIC Design Engineer (Silicon Engineering) posted Oct 10
- ASIC Design Engineer (Silicon Engineering) posted Oct 10
- Sr. ASIC Design Engineer (Silicon Engineering) posted Oct 1
- Sr. ASIC Design Engineer (Silicon Engineering) posted Oct 1
- FPGA/ASIC Design Engineer (Silicon Engineering) posted Sep 30
- FPGA/ASIC Design Engineer (Silicon Engineering) posted Sep 30
- Physical Design Engineer (Silicon Engineering) posted Sep 11
- Physical Design Engineer (Silicon Engineering) posted Sep 11
- Physical Design Engineer (Silicon Engineering) posted Sep 11
- Sr. DSP Systems Engineer (Silicon Engineering) posted Aug 13
- Sr. DSP Systems Engineer (Silicon Engineering) posted Aug 13
- ASIC/SOC DFT Engineer (Silicon Engineering) posted Aug 6
- ASIC/SOC DFT Engineer (Silicon Engineering) posted Aug 6
- Principal DFT Engineer (Silicon Engineering) posted Jul 30
- Principal DFT Engineer (Silicon Engineering) posted Jul 30
- Principal DFT Engineer (Silicon Engineering) posted Jul 30
- Sr. ASIC Design Verification Engineer (Silicon Engineering) posted Jul 14
- Sr. ASIC Design Verification Engineer (Silicon Engineering) posted Jul 14
- Sr. ASIC Design Verification Engineer (Silicon Engineering) posted Jul 14
- Sr. ASIC Design Verification Engineer (Silicon Engineering) posted Jul 14
- Design Verification Engineer (Silicon Engineering) posted Jul 14
- Design Verification Engineer (Silicon Engineering) posted Jul 14
- Design Verification Engineer (Silicon Engineering) posted Jul 14
- Design Verification Engineer (Silicon Engineering) posted Jul 14
- Site Reliability Engineer — HPC & Automation (Silicon Engineering) posted Jul 1
- Sr. Technical Project Lead (Silicon Engineering) posted Jun 26
- Sr. Technical Project Lead (Silicon Engineering) posted Jun 26
- Sr. Technical Project Lead (Silicon Engineering) posted Jun 26
- Sr. Technical Project Lead (Silicon Engineering) posted Jun 26
- Sr. Full Chip Physical Verification Engineer (Silicon Engineering) posted May 29
- Sr. ASIC DFT Engineer (Silicon) posted May 29
- Sr. ASIC DFT Engineer (Silicon) posted May 29
- Sr. ASIC DFT Engineer (Silicon) posted May 29
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) posted May 26
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) posted May 26
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) posted May 26
- Principal Design Verification Engineer (Silicon Engineering) posted May 21
- Principal Design Verification Engineer (Silicon Engineering) posted May 21
- Principal Design Verification Engineer (Silicon Engineering) posted May 21
- Principal Design Verification Engineer (Silicon Engineering) posted May 21
- Sr. Full Chip Physical Verification Engineer (Silicon Engineering) posted May 1
- Sr. Full Chip Physical Verification Engineer (Silicon Engineering) posted May 1
From the team and dates on SpaceX's own job board.
Other openings for this role
2 postings for this role in Redmond, WA since 7 March 2026, 1 still open. None has been taken down and posted again.
- 1 October 2026 – open (this posting)
- 7 March 2026 – closed
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