Senior ASIC Design Verification Engineer
- Salary
- $129,200 - $209,000 /yr
- Level
- Senior
Not stated in the posting: work type, visa.
Open. First seen 2 October 2026.
About the role
Our Mission At Palo Alto Networks®, we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea…
What this role asks for
Particular to this role
C · Perl · Unix · Verilog
Rare in Palo Alto Networks's other 299 open postings.
Standard for embedded / hardware roles
C++ · Python
Common in embedded / hardware postings at any company.
In most of Palo Alto Networks's ads
Cybersecurity
Named in most of its open postings, whatever the role.
Read against Palo Alto Networks's other open postings on this site.
Similar jobs
- Senior ASIC Design Verification Engineer at K2 Space
Shares 5 skills: Perl, Verilog, C… · Senior level · same country - Design Verification Engineer at Apple
Shares 6 skills: Perl, Verilog, C… · same country - Sr. ASIC Verification Engineer at Tensordyne
Shares 5 skills: Perl, Verilog, C… · Senior level · same country - Design Verification Engineer at Baidu USA
Shares 5 skills: Perl, Verilog, C… · Senior level · same country - Sr. Staff Engineer - Digital Design Verification at Ambiq Micro, Inc.
Shares 5 skills: Perl, Verilog, C… · same country - Senior Technical Support Engineer ( CNGFW / Cloud Security ) at Palo Alto Networks
Also at this company
Is this your posting and you want it taken down? Email info@careerholo.com.