Lead Design Engineer
- Level
- Lead
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Be part of the Cadence Memory IP Group adn responsible for - • Developing firmware for DDR/LPDDR/GDDR/HBM PHY using microcontrollers • Responsible for developing…
What this role asks for
Particular to this role
Embedded Systems
Rare in Cadence's other 299 open postings.
Standard for software engineering roles
Python
Common in software engineering postings at any company.
Read against Cadence's other open postings on this site.
Other openings for this role
10 open postings for this role in Bangalore, India, first posted 2 October 2026. The company is likely hiring for more than one position. None has been taken down and posted again.
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open (this posting)
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
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Also at this company
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