Senior Software Engineer - Low Power Verification
Hsinchu, Taiwan
- Level
- Senior
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms. What you will do…
What this role asks for
Particular to this role
VHDL
Rare in Cadence's other 299 open postings.
Standard for software engineering roles
Python
Common in software engineering postings at any company.
Compared with Cadence's other open jobs.
Similar jobs
- Sr ASIC Design Verification Engineer, Low Power AI at Qualcomm
Shares 5 skills: VHDL, Perl, Verilog… · Senior level - Senior FPGA Verification Engineer at Anduril Industries
Shares 5 skills: VHDL, Perl, Verilog… · Senior level - Embedded Software Engineer at ALTEN Technology USA
Shares 5 skills: VHDL, Perl, Verilog… - Lead Software Engineering - C++ at JPMorgan Chase
Shares 5 skills: VHDL, Perl, Verilog… - Senior Silicon Design Engineer at Microsoft
Shares 5 skills: VHDL, Perl, Verilog… · Senior level - Lead Software Engineer at Cadence
Also at this company
More jobs like this
COMPANYJobs at Cadence 331
Is this your posting? Email info@careerholo.com to have it removed.