Principal Design Engineer
Bangalore, India
- Level
- Principal
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Responsibilities • Design Verification for interconnect IP • Relevant experience in interconnect and subsystems is strongly preferred • Crafting verification plans and…
What this role asks for
Particular to this role
Unix
Rare in Cadence's other 299 open postings.
Read against Cadence's other open postings on this site.
Other openings for this role
16 open postings for this role in Bangalore, India, first posted 20 September 2026. The company is likely hiring for more than one position. None has been taken down and posted again.
- 2 October 2026 – open
- 2 October 2026 – open (this posting)
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
Similar jobs
- Senior Staff Digital Design Engineer - Audio DSP Algorithm at Syntiant
Shares 2 skills: Perl, Verilog · Staff level · same city - Principal Physical Design Engineer at Astera Labs
Shares 2 skills: Perl, Verilog · Staff level · same country - RTL Design Engineer at Weekday AI
Shares 2 skills: Perl, Verilog · same country - Senior or Staff Design Verification Engineer at Powerlattice Technologies
Shares 3 skills: Perl, Verilog, Unix · Staff level - Senior RTL Design Engineer at Envision Employment Solutions
Shares 2 skills: Perl, Verilog - Application Engineer - Custom IC at Cadence
Also at this company
Is this your posting and you want it taken down? Email info@careerholo.com.