Physical Design Engineer
- Salary
- $200K - $375K
- Level
- Senior
- Work type
- On-site · San Jose
Not stated in the posting: visa.
Open. First seen 2 October 2026.
About the role
Etched's standard text
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.
Key Responsibilities
- Deeply understand what is involved in physical design
- Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
improve CAD infrastructure
- Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
- Drive dashboards that show the convergence of projects related to PD
- Optimize tool flows, working with EDA vendors to incorporate the latest features
- Accountable for block level closure
- Supervise the outsourcing of physical design to a 3rd party service
You may be a good fit if you have
- 5-10+ years of previous experience with PD
- Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm
and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
routing, IR drop, and EM/antenna analysis
- Deeply creative and able to think from first principles
Strong candidates may also have experience with
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
- Familiarity with AI tools for programming/coding
- Startup experience or comfort working in fast-paced environments
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2.5k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch + dinner in our office
- Unlimited compute budget subject to ROI justification
How we’re different:
Etched's standard text
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
What this role asks for
Particular to this role
Machine Learning
Rare in Etched's other 103 open postings.
Standard for software engineering roles
Python
Common in software engineering postings at any company.
80% of this description is written for the role. The rest is Etched's standard text, folded away below.
Read against Etched's other open postings on this site.
The team: ASIC
This role is one of 18 open in ASIC.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (15 of 18), Machine Learning (8 of 18), Verilog (8 of 18), LLM (7 of 18), Perl (6 of 18), C (2 of 18), Embedded Systems (2 of 18)
OTHER ROLES ON THIS TEAM
- Silicon Validation Engineer, Software posted Sep 3
- Physical Design Engineer - Block Level, Subsystem Implementation posted Jul 30
- Physical Design Engineer - Full Chip Implementation posted Jul 23
- Physical Design Engineer - Flow & Methodologies posted Jul 23
- Physical Design Engineer - Block Level, Subsystem Implementation posted Jul 23
- Product Engineer, Silicon Validation posted May 6
- ASIC Technical Program Manager posted May 1
- Physical Design Engineer posted Apr 16
- Design Verification Engineer - SoC posted Apr 16
- Design Verification Engineer - Internal IP posted Apr 16
- Design Verification Engineer - Interface IP posted Apr 16
- DFT (Design For Test) Engineer posted Feb 28
- Post-Silicon Validation Engineer posted Oct 13
- Design Verification Engineer - Interface IP posted Sep 11
- Design Verification Engineer - SoC posted Sep 11
- RTL Design Engineer posted Jun 11
- Design Verification Engineer - Internal IP posted Jun 11
From the team and dates on Etched's own job board.
Salary context
8 other open postings titled Physical Design Engineer state a salary: median USD 190,000 to USD 310,000 a year.
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