Product Application Engineer PCIe/CXL
- Salary
- $185,000 - $240,000
- Level
- Senior
Not stated in the posting: work type, visa.
Open. First seen 2 October 2026.
About the role
Astera Labs's standard text
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
As an Astera Labs Principal Product Application Engineer, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes.
Astera Labs is seeking a Principal Product Applications Asia Region Lead with 8+ years of experience supporting the development and design-in of semiconductor products for PCIe/CXL. Regional leads focus on development, debugging, and design-in activities related to customers in a designed geography, and help coordinate with local development teams in Astera Labs Headquarters. This role will be supporting our China region. Role is required to work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone.
Basic Qualifications
- Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, Master’s is preferred.
- Minimum of 3 years’ experience in designing in complex SoC/silicon products with a high speed (preferably PCIe) interface.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind!
- Full professional proficiency in Mandarin (written and spoken) required to communicate directly with Asia region customer contacts
Required Experience
- Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug. Most recent experience with PCIe 5.0 at a minimum, some experience with 6.0/CXL preferred.
- Silicon/System bring-up and debug experience in customer systems.
- Technical ownership of issue resolution: Driving and directing internal teams toward issue resolution. Driving communication with customers, FAEs, and sales team members
- Firsthand experience with lab equipment such as protocol analyzers/exercisers, high-speed oscilloscopes, or BERTs.
- Comfort working with software/firmware associated with semiconductor products, such as: Firmware development with C-language, scripting with Python or other equivalent programming languages.
Preferred experience
- Triaging complex customer reported issues which require taking into account multiple layers of conditions. For instance, silicon, firmware, hardware board design, and system environment.
- Experience with common data center BMC implementation, and BIOS configuration
- Development/support for PCIe or Ethernet Switch or Retimer products.
- PCIe compliance testing methodology and troubleshooting.
- Understanding of Data Center systems like Servers, JBOGs/JBODs, Networking switches/routers/interconnects etc.
- Mandarin language proficiency preferred. Candidate must be able to speak Mandarin to effectively communicate with our China region customers and team members.
- Candidate will need to be open work approximately from 12:00 PM to 9:00 PM PST to enable real-time collaboration with stakeholders in the Asia Pacific time zone
Base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
Astera Labs's standard text
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
What this role asks for
Standard for software engineering roles
Python
Common in software engineering postings at any company.
77% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.
Compared with Astera Labs's other open jobs.
The team: Product Applications HIRES STEADILY
This role is one of 10 open in Product Applications. 3 were posted in the last 30 days and the oldest in April: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Embedded Systems (9 of 10), Python (8 of 10), C (4 of 10), C++ (3 of 10), Linux (3 of 10), Test Automation (3 of 10)
OTHER ROLES ON THIS TEAM
- Principal Product Applications Engineer – Scorpio posted Oct 7
- AE| Principal Product Application Engineer (Scorpio) posted Sep 29
- Principal Product Applications Engineer posted Sep 22
- Principal Product Applications Engineer - Scorpio posted Aug 18
- Sr. Principal Product Applications Engineer – Custom Solutions posted Aug 14
- Senior Tools Development Engineer – COSMOS Platform Software posted Aug 11
- Principal Product Application Engineer - PCIe posted May 20
- Applications Engineering Manager - Ethernet posted May 20
- Principal Product Applications Engineer – Memory & CXL posted Apr 29
From the team and dates on Astera Labs's own job board.
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