Hardware Engineer (FPGA)
- Level
- Mid
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
Virtu is a leading financial firm that leverages cutting edge technology to deliver liquidity to the global markets and innovative, transparent trading solutions to our clients. As a market maker, Virtu provides deep liquidity that helps to create more efficient markets around the world. Our market structure expertise, broad diversification, and execution technology enables us to provide competitive bids and offers in over 19,000 securities, at over 235 venues, in 36 countries worldwide.
THE ROLE
Virtu's Hardware Design team builds the FPGA and ASIC applications at the core of the firm's proprietary low-latency trading platform.
We are looking for an FPGA/ASIC Engineer to join us. The ideal candidate will be a creative and ambitious hardware engineer who is excited to work on our low-latency trading infrastructure. You'll work on challenging problems alongside a small, international team.
In this role you will:
- Design and develop RTL for new low-latency trading applications
- Own designs end to end, from specification through verification to production deployment
- Improve the team's build, simulation, and verification infrastructure
- Coordinate and execute hardware deployments in live production environments
Virtu offers a dynamic, meritocratic environment with a flat hierarchy. No finance background is necessary or expected. This is a great opportunity for the right candidate to start a career in the financial technology space.
THE CANDIDATE
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related field
- 2+ years of professional FPGA or ASIC experience (an advanced degree may substitute)
- Strong RTL design and verification skills (SystemVerilog/VHDL, cocotb)
- Familiarity with FPGA/IC design flows and vendor toolchains (Xilinx/AMD, Synopsys, Cadence)
- Working knowledge of high-speed interfaces (Ethernet/MAC/PHY, PCIe, AXI)
DESIRED BUT NOT REQUIRED
- Programming in Python, C++, or similar
- Back-end physical design experience
- Understanding of network protocols and packet processing (TCP/UDP, IP multicast, and hardware protocol offloading)
BENEFITS
- Generous Time Off: 26 days annual leave, plus additional leave for community service, marriage/civil partnerships, and moving house
- Family Support: Paid maternity leave and enhanced paternity leave
- Comprehensive Health & Wellbeing: Private health, dental, and optical cover, GP access, and a dedicated wellness programme
- Financial Protection: Life assurance, income protection, and a competitive pension scheme
- Active Lifestyle Perks: Gym subsidy/fitness reimbursement and Cycle to Work scheme
- Commuting Made Easy: Commuter benefit plan
- Travel Cover: Personal travel insurance
- Daily Perks: Complimentary catered lunches every day, laundry service, onsite gym, barber and hairdresser service
THE PROCESS
After passing an initial application screening, candidates will complete an online assessment via HackerRank as the first stage of the process. After passing the online test, we will contact you to arrange a phone screen.
Virtu Financial's standard text
Virtu Financial is an equal opportunity employer, committed to a diverse and inclusive workplace, welcoming you for who you are and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status.
What this role asks for
Standard for embedded / hardware roles
C++
Common in embedded / hardware postings at any company.
In most of Virtu Financial's ads
Python
Named in most of its open postings, whatever the role.
90% of this description is written for the role. The rest is Virtu Financial's standard text, folded away below.
Read against Virtu Financial's other open postings on this site.
The team: Technology HIRES STEADILY
This role is one of 10 open in Technology. 1 was posted in the last 30 days and the oldest in April: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Java (8 of 10), Python (7 of 10), C++ (6 of 10), .NET (2 of 10), C# (2 of 10), CSS (2 of 10), Git (2 of 10)
OTHER ROLES ON THIS TEAM
- Electronic Trading Engineer posted Oct 9
- Electronic Trading Engineer (Retail Routing) posted Sep 18
- Software Engineer - Desktop Frontend Developer (C#/Winforms) posted May 4
- Machine Learning Engineer posted Mar 10
- Full Stack Developer posted May 5
- Software Engineer - Client Trading Infrastructure (Java) posted Apr 18
- Core Developer - China Desk posted Mar 12
- Software Engineer - Web Application, Front-end (Javascript/React) posted Dec 2
- Software Engineer - Frontend Trading Application (C#/.NET) posted Apr 12
From the team and dates on Virtu Financial's own job board.
Similar jobs
- Hardware Engineer, FPGA at Normal Computing Corporation
Shares 5 skills: VHDL, Verilog, FPGA… · same seniority - FPGA Engineer at ALTEN Technology USA
Shares 5 skills: VHDL, Verilog, FPGA… · same seniority - Embedded Systems Engineer - FPGA Platform at Infleqtion
Shares 5 skills: VHDL, Verilog, FPGA… · same seniority - Senior FPGA Engineer (VHDL/Verilog) at AGAD Technology
Shares 5 skills: VHDL, Verilog, FPGA… - Senior FPGA RF Signal Processing Engineer at Muon Space
Shares 5 skills: VHDL, Verilog, FPGA… - Weekend Systems Engineer at Virtu Financial
Also at this company
Is this your posting and you want it taken down? Email info@careerholo.com.