Senior FPGA Engineer - Systems Team
- Salary
- £70,000 - £108,000
- Level
- Senior
Not stated in the posting: work type, visa.
Open. First seen 3 October 2026.
About the role
Senior FPGA Engineer – Systems Team
Cambridge, UK | Full-time | Permanent | Hybrid
Salary: £70,000 to £108,000, DOE
The salary range for this role is broad, as we are able to consider varying levels of experience. Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements.
We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.
About us
Riverlane's standard text
Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved. Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.
Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.
About the role
Systems Engineering bridges the gap between Riverlane and its customers. They act as the primary technical interface for our customers’ engineers to guide them through product integration and help with troubleshooting complex quantum systems. They are key to securing design wins and driving product development.
As an FPGA Engineer, you will configure our Deltaflow Hardware to connect Quantum Computers to provide low-latency, high throughput systems that perform complex operations in a predictable and guaranteed way. You will use your knowledge and expertise to adapt the hardware to an ever-changing quantum control system to support scientists that are running quantum experiments.
This is a fantastic opportunity to join Riverlane’s team, that is developing the world’s most advanced quantum error correcting algorithms. The Riverlane team is a mix of mathematicians, physicists and engineers, working together on a range of exciting and cutting-edge projects.
What you will do:
Technical pre-Sales:
- Host Technical Workshops on Riverlane’s QEC Interface
- Evaluate Customers Control System and Data Communication requirements.
Integration On-Site: End-to-End System Deployment:
- Writing RTL to adapt to customers control systems and ensure data packets are received correctly.
- Work with Riverlane’s Quantum Application Team to design experiments to test the system.
- Benchmark and discover hardware latency limitations.
Troubleshooting and Debugging: Managing Customer Issues:
- Report issues and help replicate the setup with the QA team in Riverlane.
- Writing script to debug and trace faults
- Update verification environment and the test vectors based on data gathered from the experiments that were conducted.
Customer Advocacy: Voice of the Customer to Riverlane Product Team:
- Highlight the success, issues and trends on customer’s Quantum Systems
- Feedback key features that will be needed to win current and next generation products
What we need:
- Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)
- Experience in writing SystemVerilog or VHDL
- Proven professional experience in at least one of the following areas:
- Implementation of modern classical decoders on FPGA e.g. LDPC, turbo-codes;
- Implementation of Ethernet and High-Speed Protocols
- Implementation of customs protocols and standards.
- Proven capability to test, debug and improve UVM Verification Environment.
- Good knowledge of Python and C++
- Ability to convert product requirements into technical specifications to document and share your work
- A curious nature and a passion for learning and continuous improvement
- Excellent communication skills, with the ability to work both independently and collaboratively as part of a team
Typically, our Senior FPGA Engineers have around 4–8 years of relevant experience, though this can vary by background.
Even better if you have:
- Experience of working on scientific instrumentation
- PhD in a relevant subject
- Good knowledge of quantum mechanics.
What can you expect from us:
- A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme
- Equity, so that our team can share in the long-term success of Riverlane
- 28 days annual leave, plus bank holidays and enhanced family leave
- A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
- A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets
How to apply
Please upload a CV and covering letter by clicking 'Apply Now'. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role.
Riverlane's standard text
We review CVs as we receive them and interview as soon as we have applications that look like a good match. We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role.
If you have any queries, please contact jobs@riverlane.com.
#LI-KW1
Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.
Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements. If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you.
If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.
What this role asks for
Particular to this role
FPGA · VHDL
Rare in Riverlane's other 15 open postings.
In most of Riverlane's ads
C++ · Python
Named in most of its open postings, whatever the role.
73% of this description is written for the role. The rest is Riverlane's standard text, folded away below.
Read against Riverlane's other open postings on this site.
The team: Engineering HIRES STEADILY
This role is one of 10 open in Engineering. 2 were posted in the last 30 days and the oldest in February: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
C++ (10 of 10), Python (10 of 10), Rust (4 of 10), Verilog (4 of 10), Embedded Systems (3 of 10), VHDL (3 of 10)
OTHER ROLES ON THIS TEAM
- Senior Embedded Software Engineer - Systems Team posted Oct 13
- Director of Open-Source Software posted Sep 28
- Software Tech Lead posted Jul 24
- Senior Compiler Engineer - Systems Team posted Jun 11
- Senior Embedded Software Engineer - Systems Team posted Jun 5
- Senior Software Engineer - Open Source posted May 28
- Compiler Engineer posted Feb 17
- Senior Compiler Engineer posted Feb 17
- Verification / Senior Verification Engineer posted Feb 4
From the team and dates on Riverlane's own job board.
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