Avionics Design Engineer

Logos Space is building the world's first Low Earth Orbit (LEO) satellite network with built-in capacity and resilience from day one. We are defining a new category—Provable Path Independence—delivering assured, high-performance broadband and cloud network connectivity to enterprise and government customers operating in the world's most demanding environments. Led by veteran aerospace and networking engineers, Logos is building hardware engineered to perform under any condition.

The Role & Impact

As a Avionics Design Engineer at Logos, you will not just draw schematics—you will architect, build, and field high-bandwidth flight processing units and avionics that power our next-generation LEO constellation. You will own flight hardware across its entire lifecycle, taking vague, complex design concepts and translating them into flight-ready hardware that survives and thrives on-orbit.

Key Responsibilities

• End-to-End Design Ownership: Architect and design flight avionics, high-speed processing boards, and payload digital systems from initial architecture through schematic capture, layout guidance, and bring-up.
• Advanced Analysis: Conduct Signal Integrity (SI), Power Integrity (PI), Worst-Case Circuit Analysis (WCCA/Monte Carlo), and Parts Stress/Derating analysis to guarantee high-reliability performance in space.
• Cross-Functional Collaboration: Partner directly with Flight Software, RF, Mechanical, and Thermal engineering teams to optimize system-level tradeoffs, board pinouts, and physical packaging.
• Manufacturing & Bring-Up: Collaborate with Contract Manufacturers (CMs) for DFM/DFA reviews, PCBA assembly oversight, rapid prototyping, and hands-on lab troubleshooting.
• Validation & Flight Qualification: Generate comprehensive technical drawings, specifications, test procedures, and reports; lead board-level and system-level environmental testing (thermal vacuum, vibration, EMI/EMC).

Basic Qualifications

• Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related STEM field.
• Experience: 5+ years of hands-on experience in digital electrical design and hardware analysis.
• High-Speed Interfaces: Proven experience designing with high-speed digital interfaces (e.g., DDR4/DDR5, 1G/10G Ethernet, PCIe) and standard communication buses (CAN, RS-422/RS-485, SPI, I2C).
• SI/PI Analysis: 3+ years of hands-on experience using Signal and Power Integrity modeling tools (e.g., Ansys SIwave, HyperLynx).
• ECAD Proficiency: Advanced design experience with professional schematic capture and PCB layout tools (preferably Altium Designer).
• Space / High-Reliability Rigor: Demonstrated track record with Worst-Case Analysis (WCCA), parts stress evaluation, and derating.
• Lab Equipment Mastery: Deep proficiency with lab diagnostic tools (oscilloscopes, logic analyzers, spectrum analyzers, power supplies).
• U.S. Person Status: Must be a U.S. Citizen or Permanent Resident due to export control regulations (ITAR/EAR).

Preferred Qualifications

• Master's degree in Electrical Engineering or STEM field.
• Experience designing high-density FPGA or SoC processing systems for space or aerospace applications.
• Familiarity with industry space derating and design standards (e.g., EEE-INST-002, ECSS-Q-ST-30-11C, IPC-2221).
• Hands-on experience with circuit simulation software (LTSpice, SIMetrix/SIMPLIS).
• Knowledge of EMI/EMC/ESD design mitigations and testing protocols for space flight hardware.
• Scripting and test automation skills using Python or MATLAB.
• Ability and willingness to obtain and maintain a U.S. Government Top Secret Security Clearance.

Engineering Culture & Benefits

• Fast Iteration Cycles: In-house rapid prototyping and dedicated test lab access to validate designs quickly.
• Ownership & Autonomy: No silos, no politics—we encourage debate, make data-driven decisions fast, and commit together.
• Location Flexibility: On-site opportunity in either Mountain View, CA or San Diego, CA with relocation support available.

This policy applies with regard to all aspects of one's employment, including hiring, transfer, promotion, compensation, eligibility for benefits, and termination. Offers will be contingent on the candidate's ability to access export-controlled information under U.S. law.