Physical Design Engineer

Summary Description:

Syntiant Corp., a leader in the high-growth AI software and semiconductor solutions space, is looking for an experienced and talented Physical Design Engineer to take on a critical role with expansive responsibilities to enhance the Hardware Engineering function in a growing organization.

As Physical Design Engineer, you will be a key player in the ASIC R&D team. You are presented with a unique opportunity to drive the complete physical design flow, from RTL-to-GSDII to achieve best in class PPA for the next generation Syntiant ASICs while working in a cross-functional environment interacting with multiple teams.

Requirements

Specific Duties and Responsibilities:

• Drive next generation physical design work to achieve best in class PPA for Syntiant’s next generation ASICs.
• RTL to GDSII Physical Design Implementation, including Synthesis, Pad Ring, Floorplan, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification.
• Work with Physical Verification Team to clean-up layout violations.
• Work with foundry to complete tape-out related forms and checks.

Qualifications, Education, and Experience Required:

• Advanced degree in electronics engineering with 5+ years’ experience in physical design and implementation.
• Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff with a focus on improving PPA (Performance, Power, Area).
• Deep knowledge on industry standards and practices in physical design including physically aware synthesis flow, floor-planning, place & route, metal fill, chip finishing, signal integrity checks, and static/dynamic EMIR-Drop analysis, and formal ESD verification.
• Experience in building chip floorplan including partitions and power grid.
• Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations.
• Experience in physical design verification to debug & fix LVS/DRC/PERC issues at the chip/block level using industry standard tools.
• Experience in UPF flow.
• Experience in tape-out related communication with foundry (forms, jobview, etc).
• Experience in package, RDL routing design.
• Experience with Programming/scripting languages (e.g., Python or Perl, tcl).
• Experience with scan insertion and ATPG pattern generation is a plus.
• Experience with power analysis flows is a plus.

Benefits

About Syntiant:

One element in our total compensation package is base pay. Individual compensation decisions are based on several factors, including but not limited to previous experience and skills acquired prior to joining Syntiant, cost of living in the assigned work location, assigned schedule, and salaries of similarly situated peers at the company. It is to be expected that candidates will come to us with different sets of skills and experiences and therefore will be paid at different points in the stated range.

We recognize that the person(s) we select for hire may be less experienced or more experienced than the role as posted; if this is the case, any updates to available salary ranges will be communicated with candidates during the recruitment process.