Low-Power Design Engineer
- Level
- Mid
Not stated in the posting: salary, work type, visa.
Open. First seen 19 October 2026.
About the role
Voltai's standard text
About Voltai
Voltai is developing world models, and agents to learn, evaluate, plan, experiment, and interact with the physical world. We are starting out with understanding and building hardware; electronics systems and semiconductors where AI can design and create beyond human cognitive limits.
About the Team
Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc. We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents.
About this Role
You'll own power intent from architecture through signoff. You'll design and verify low-power architectures on real silicon programs with leading semiconductor companies while helping Voltai's AI learn power-aware design.
What You’ll Do
- Define power architecture and write UPF power intent for SoCs and IP.
- Implement and verify power gating, clock gating, multi-voltage domains, and retention.
- Run power-aware simulation, static low-power checks, and CDC/RDC analysis.
- Partner with RTL, physical design, and signoff teams on power estimation and closure.
- Build automation for power analysis and reporting.
- Evaluate AI-generated power intent and help define what correct looks like.
What We’re Looking For
- 5+ years of low-power design or verification experience on production tapeouts.
- Expert UPF knowledge and experience with power-aware verification.
- Hands-on experience with tools like VC LP, Conformal Low Power, or PowerArtist.
- Experience with CDC/RDC tools (SpyGlass, Questa CDC, or similar).
- Python or Tcl scripting.
Bonus Points
- Experience with mobile, edge, or data-center power management.
- Formal verification of power intent.
- Interest in AI-assisted design tools.
What this role asks for
Standard for software engineering roles
Python
Common in software engineering postings at any company.
85% of this description is written for the role. The rest is Voltai's standard text, folded away below.
Compared with Voltai's other open jobs.
The team: Chips & Silicon HIRES STEADILY
This role is one of 12 open in Chips & Silicon. 10 were posted in the last 30 days and the oldest in November: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (11 of 12), C++ (3 of 12), Verilog (3 of 12), C (2 of 12), Machine Learning (2 of 12)
OTHER ROLES ON THIS TEAM
- Post-Silicon Validation Engineer posted Oct 19
- Design for Test (DFT) Engineer posted Oct 19
- CAD & Flow Methodology Engineer posted Oct 19
- Physical Verification & Signoff Engineer posted Oct 19
- Emulation & FPGA Prototyping Engineer posted Oct 19
- Physical Design Engineer posted Oct 19
- Synthesis & Static Timing Analysis (STA) Engineer posted Oct 19
- RTL Design Engineer posted Oct 19
- Chip Architect posted Oct 19
- Formal Verification Engineer posted Nov 12
- Design Verification Engineer posted Nov 12
From the team and dates on Voltai's own job board.
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