SOC Design Verification Engineer
- Salary
- $121,800 - $182,600
- Level
- Mid
- Work type
- On-site · San Diego
Not stated in the posting: visa.
Open. First seen 26 October 2026.
About the role
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: We are seeking highly motivated and experienced Design Verification Engineers to join our Data Center SoC Verification team. In this role, you will be…
What this role asks for
Particular to this role
Verilog
Rare in Qualcomm's other 145 open postings.
In most of Qualcomm's ads
Python
Named in most of its open postings, whatever the role.
Compared with Qualcomm's other open jobs.
The team: ASICS Engineering
This role is one of 40 open in ASICS Engineering. 40 were posted in the last 30 days.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (19 of 40), C (14 of 40), Verilog (12 of 40), C++ (9 of 40), Perl (9 of 40), FPGA (8 of 40), Embedded Systems (6 of 40)
OTHER ROLES ON THIS TEAM
- Tech IP Library Characterization Engineer posted Oct 8
- Physical Design Engineer, Sr. Staff posted Oct 8
- Staff Emulation Build Quality, Performance & Debug Engineer posted Oct 8
- Emulation Performance Methodology & Debug Engineer posted Oct 8
- Senior Emulation Performance Methodology & Debug Engineer posted Oct 8
- ASICS Design Verification Engineer (Vancouver, Markham OR Remote) posted Oct 8
- Next Gen, High-Speed, Memory and Cache Controller Design Engineer posted Oct 7
- Firmware Engineer, Edge AI Silicon Validation (Embedded C) posted Oct 7
- Front-End Implementation Engineer (Staff) (Timing & Synthesis)- Cork, Ireland posted Oct 7
- Memory Designer posted Oct 7
- ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham posted Oct 7
- Design Engineer - Hod Hasharon posted Oct 7
- SOC Design Verification Engineer posted Oct 7
- Director , Engineering (GPU Physical Design) posted Oct 7
- Hardware Verification, Engineer at Qualcomm Interconnect Technology Center (QITC) - France posted Oct 7
- Next-Gen System Cache ASIC Digital Design Engineer posted Oct 7
- EDA/CAD Software Engineer, Staff posted Oct 7
- Memory Circuit Design Engineer posted Oct 7
- DDRSS Systems Engineer posted Oct 7
- BEOL Process Integration Engineer, up to Sr. Staff posted Oct 6
- SOC Debug Engineer posted Oct 6
- PMIC Design Verification Lead (Sr Staff Engineer) posted Oct 6
- Silicon Validation Senior Engineer posted Oct 6
- High-Bandwidth Memory (HBM) System Validation Lead (AI Accelerator Platform) posted Oct 6
- SOC Design Verification Staff Engineer posted Oct 5
- Camera Frontend Implementation Engineer posted Oct 5
- Architecture/System Validation Engineer posted Oct 2
- Physical Design (Multiple levels) posted Oct 2
- Systems Engineer (ML and DSP) - Cork, Ireland posted Oct 2
- SOC Design Verification Engineer posted Oct 2
- Physical Design Engineer posted Oct 2
- VLSI Frontend CAD Applications Engineer posted Oct 2
- DFT-Staff Engineer posted Oct 2
- Foundry Engineer for Advanced Technology (Device/Process/ Product) posted Oct 2
- Staff Analog IC Design Engineer (ADC) posted Oct 1
- Staff RF Hardware Engineer - Device Technology posted Oct 1
- Physical Design Engineer, Staff - Hod Hasharon posted Oct 1
- Design Verification Engineer - NPU- Engineer to Sr. Staff Engineer posted Oct 1
- SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team posted Oct 1
From the team and dates on Qualcomm's own job board.
Other openings for this role
3 open postings for this role in San Diego, California, United States of America, first posted 26 October 2026. The company is likely hiring for more than one position. None has been taken down and posted again.
- 26 October 2026 – open
- 26 October 2026 – open (this posting)
- 26 October 2026 – open
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