Design Verification Engineer
- Salary
- $102,100 - $202,200 per year
- Level
- Mid
- Work type
- On-site · North Carolina
Not stated in the posting: visa.
Open. First seen 28 October 2026.
About the role
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational…
What this role asks for
Particular to this role
Embedded Systems · Perl · Ruby · Verilog
Rare in Microsoft's other 299 open postings.
Standard for software engineering roles
Python
Common in software engineering postings at any company.
Compared with Microsoft's other open jobs.
The team: Silicon Engineering HIRES STEADILY
This role is one of 35 open in Silicon Engineering. 31 were posted in the last 30 days and the oldest in June: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Azure (34 of 35), Microsoft 365 (34 of 35), Python (18 of 35), Embedded Systems (11 of 35), C++ (10 of 35), Verilog (10 of 35), C (9 of 35)
OTHER ROLES ON THIS TEAM
- Senior SoC HW Analog/Functional Validation Engineer posted Oct 26
- Principal SoC HW Analog/Functional Validation Engineer posted Oct 26
- Principal Package Engineer posted Oct 26
- Senior CAD Software Engineer posted Oct 26
- Senior Physical Design Engineer posted Oct 22
- Senior Silicon Engineer posted Oct 22
- Senior SoC HW (Power & Performance) Validation Engineer posted Oct 21
- Senior Principal Power Management Architect posted Oct 21
- Logic Design Engineer posted Oct 21
- Principal Physical Design Engineer posted Oct 20
- Senior Physical Design Engineer posted Oct 20
- Principal Silicon Design Verification Engineer posted Oct 20
- Senior Silicon Engineer posted Oct 20
- Principal Design Verification Engineer posted Oct 20
- Principal Silicon Design Verification Engineer posted Oct 20
- Silicon Physical Design CAD Engineer posted Oct 15
- Senior SOC Integration Engineer posted Oct 14
- Senior Silicon Design Engineer posted Oct 14
- Principal SOC Performance Verification Engineer posted Oct 14
- Senior Software CAD DevOps Engineer posted Oct 13
- Senior FPGA/Silicon Design Engineer posted Oct 13
- Director of Package Design posted Oct 13
- Senior Silicon CAD Software Engineer posted Oct 13
- Test Engineer (Silicon Engineering) posted Oct 13
- Silicon Debug Engineer posted Oct 12
- Senior Packaging Engineer posted Oct 12
- Signal and Power Integrity Engineer posted Oct 8
- Design Verification Engineer - DDR Memory Subsystem posted Sep 30
- Physical Design Engineer II posted Sep 30
- Senior IP Design Verification Engineer posted Sep 29
- Director, Silicon Physical Design CAD posted Aug 5
- Principal Silicon Systems Architect posted Jul 28
- Principal Silicon Engineer posted Jul 22
- Principal Signal and Power Integrity Engineer posted Jun 2
From the team and dates on Microsoft's own job board.
Posting history
Reposted once since 26 October 2026: a posting for this role in United States, North Carolina, Raleigh was taken down and the role was posted again.
- 28 October 2026 – open (this posting)
- 26 October 2026 – closed 27 October 2026
Salary context
17 other open postings titled Design Verification Engineer state a salary: median USD 175,000 to USD 308,500 a year.
Similar jobs
- Senior ASIC Design Verification Engineer at K2 Space
Shares 6 skills: Perl, Verilog, C… · same country - ASICS Design Verification Engineer at Qualcomm
Shares 5 skills: Perl, Verilog, C… · same country - Embedded Software Engineer at ALTEN Technology USA
Shares 6 skills: Perl, Verilog, C… · same seniority · same country - FPGA Engineer (Starshield) at SpaceX
Shares 6 skills: Perl, Verilog, C… · same seniority · same country - Senior FPGA Verification Engineer at Anduril Industries
Shares 5 skills: Perl, Verilog, Embedded Systems… · same country - Customer Solution Engineer at Microsoft
Also at this company
More jobs like this
Is this your posting? Email info@careerholo.com to have it removed.