Sr/Staff Engineer, Design Verification,System IP
- Level
- Staff
- Work type
- Hybrid · Bengaluru
Not stated in the posting: salary, visa.
Open. First seen 25 May 2026.
About the role
Tenstorrent's standard text
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.
We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure.
This role is hybrid, based out of Bangalore, India.
Tenstorrent's standard text
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM.
- You enjoy debugging complex design and verification issues and working closely with cross-functional teams.
- You’re comfortable building verification environments from scratch and driving coverage closure.
- You have familiarity with standard bus protocols and modern verification tools.
What We Need
- Experience owning block or subsystem-level verification from test planning to sign-off.
- Strong understanding of constrained-random verification, coverage analysis, and regression debugging.
- Familiarity with protocols such as AXI, ACE, CHI, or PCIe.
- Scripting experience in Python, Perl, TCL, or Bash for automation and workflow improvements.
What You Will Learn
- Verification of advanced CPU and memory-management related IPs used in AI/ML systems.
- Building scalable UVM environments and improving verification methodologies.
- Collaborating across architecture, RTL, and validation teams throughout the development cycle.
- Using Automation and AI-assisted tools to improve productivity and debug efficiency
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).
These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.
Tenstorrent's standard text
If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
What this role asks for
Standard for software engineering roles
Python
Common in software engineering postings at any company.
71% of this description is written for the role. The rest is Tenstorrent's standard text, folded away below.
Read against Tenstorrent's other open postings on this site.
The team: RISC V HIRES STEADILY
This role is one of 8 open in RISC V. 1 was posted in the last 30 days and the oldest in October: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (4 of 8), Bash (2 of 8), C (2 of 8), C++ (2 of 8), Verilog (2 of 8)
OTHER ROLES ON THIS TEAM
- Sr. Engineer, Performance Infrastructure (RISC-V) posted Sep 24
- CPU Core Design Verification Manager posted Sep 8
- System IP RTL Design Lead posted May 27
- CPU Core Design Verification Testbench Lead posted May 22
- Staff Engineer, CPU Core Verification posted May 20
- CPU Core Design Verification Test Generator Lead posted May 15
- Engineering Program Manager, RISCV posted Oct 22
From the team and dates on Tenstorrent's own job board.
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