Sr Principal Design Engineer
Bangalore, India
- Level
- Principal
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description: • RTL Design Engineer for DDR Memory Controller IP development team. • The role would include the design and support of the RTL of the DDR Memory…
Posting history
Reposted once since 20 September 2026: a posting for this role in Bangalore, India was taken down and the role was posted again.
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open (this posting)
- 2 October 2026 – open
- 2 October 2026 – open
- 2 October 2026 – open
- 20 September 2026 – closed 29 September 2026
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