Design Verification Engineer
- Salary
- $200 - $400,000
- Level
- Senior
- Work type
- Hybrid · New York
Not stated in the posting: visa.
Open. First seen 2 October 2026.
About the role
Normal Computing Corporation's standard text
Normal Computing | Build with Us
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
The Role
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done.
This is a seat for a verification engineer who wants their craft to compound rather than repeat.
What You Will Own
- Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
- AI Product Refinement: Review AI-generated verification collateral to shape product strategy and tool usability in collaboration with the ML and product teams.
- Data Quality Bar: Set the quality standard for verification training data: define rubrics, curate golden examples, and partner with our Data team, who own the pipelines, so our models learn from verification artifacts a real DV engineer would sign off on.
- Deployment Support: When needed, support customer engagements alongside our forward-deployed team: validating AI-generated collateral against real customer specifications and lending DV credibility to deployments.
- Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally and in customer environments.
What Makes You a Great Fit
- 5+ years of experience in digital verification at a major semiconductor or EDA tool company
- Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
- Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
- Willingness to occasionally support customer-facing deployment work, including some travel
- Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session
Bonus Points
- Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
- Hands-on use of LLMs or agentic tools in verification workflows
- Exposure to analog, mixed-signal, or unconventional compute verification
Normal Computing Corporation's standard text
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.
What this role asks for
Particular to this role
Perl
Rare in Normal Computing Corporation's other 19 open postings.
In most of Normal Computing Corporation's ads
Python
Named in most of its open postings, whatever the role.
68% of this description is written for the role. The rest is Normal Computing Corporation's standard text, folded away below.
Read against Normal Computing Corporation's other open postings on this site.
The team: Silicon Chip / ASIC HIRES STEADILY
This role is one of 4 open in Silicon Chip / ASIC. 1 was posted in the last 30 days and the oldest in July: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (3 of 4), Verilog (3 of 4), FPGA (2 of 4), LLM (2 of 4), Perl (2 of 4)
OTHER ROLES ON THIS TEAM
- Hardware Engineer, FPGA posted Oct 14
- Hardware Engineer, RTL posted Aug 10
- Hardware Engineer, PCB posted Jul 29
From the team and dates on Normal Computing Corporation's own job board.
Salary context
22 other open postings titled Design Verification Engineer state a salary: median USD 175,000 to USD 308,500 a year.
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