Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)
- Level
- Staff
Not stated in the posting: salary, work type, visa.
Open. First seen 3 October 2026.
About the role
SK hynix memory solutions America Inc.'s standard text
About the Company:
At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.
We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices.
As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.
About the Team
You will join the System on Chip (SoC) Design Team at SK Hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Staff Engineer, you will own critical High speed interface IP, drive methodology improvements (such as AI-assisted design flows), and mentor engineers to ensure first-pass silicon success.
Responsibilities
- Design and verification of the high speed interface for next generation storage subsystem for NVME or Chiplet.
- Drive team efforts with multi-function teams from RTL development through silicon bring-up.
Minimum Qualifications
- 3 - 7 years of experience in ASIC design.
- Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
- Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
- Experience with Clock Domain Crossing (CDC), timing closure, synthesis flows or Gate Level Simulation(GLS).
Preferred Qualifications
- Experience in PCle(Gen4/5/6) architecture in TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
- Proven experience with Link training, power state(L0/L0P/L1/L2), error handling (AER).
- Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
- Good plus to have experience in AI Assist design flow.
Education
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
REGARDING COMPENSATION:
SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth.
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.
What this role asks for
Particular to this role
Perl · Verilog
Rare in SK hynix memory solutions America Inc.'s other 24 open postings.
Standard for embedded / hardware roles
Python
Common in embedded / hardware postings at any company.
In most of SK hynix memory solutions America Inc.'s ads
Machine Learning
Named in most of its open postings, whatever the role.
65% of this description is written for the role. The rest is SK hynix memory solutions America Inc.'s standard text, folded away below.
Read against SK hynix memory solutions America Inc.'s other open postings on this site.
The team: System on Chip (SoC) HIRES STEADILY
This role is one of 6 open in System on Chip (SoC). 4 were posted in the last 30 days and the oldest in April: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Machine Learning (6 of 6), Python (6 of 6), Perl (3 of 6), ANSYS (2 of 6), FPGA (2 of 6), Verilog (2 of 6)
OTHER ROLES ON THIS TEAM
- Physical Design Engineer posted Oct 7
- Research Intern - Loop Engineering posted Oct 6
- Research Scientist - Loop Engineering and AI Infrastructure posted Oct 2
- Sr. Staff / Principal Physical Design Engineer posted Sep 26
- Embedded Software Engineer Intern posted Sep 12
From the team and dates on SK hynix memory solutions America Inc.'s own job board.
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