Digital Design Engineers - 7 openings
- Level
- Senior
- Work type
- Hybrid · Hyderabad
Not stated in the posting: salary, visa.
Open. First seen 22 October 2026.
About the role
Kandou AI's standard text
At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems - a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, Chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency - unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement - it’s a foundational shift in how AI hardware is built for the future.
Location: Bangalore OR Hyderabad
Department: Semiconductor Design Engineering
Experience Level: 5–10 Years
Employment Type: Full-Time
About the Role:
We are seeking for talented Mid-Level Digital Design Engineers to contribute to the development of high-performance digital circuits for next-generation communication and memory interfaces. The ideal candidate will have strong experience in high-speed digital design, semiconductor development flows, and cross-functional collaboration with verification and analog/mixed-signal teams.
Key Responsibilities:
- Define digital architecture concepts and specify analog-to-digital interfaces.
- Develop RTL for high-speed digital blocks and contribute to IP verification and basic DFT implementation.
- Perform logic synthesis and support timing analysis activities.
- Design and verify high-performance digital circuits meeting area, timing, and power requirements.
- Develop block-level specifications based on system-level requirements.
- Collaborate closely with verification, physical implementation, and analog/mixed-signal engineering teams.
- Analyse and implement high-speed serial protocols (e.g., USB4, PCIe).
- Support post-silicon bring-up, debugging, characterization, and productization.
- Validate and test silicon in laboratory environments.
Required Qualifications:
- B.E/B.Tech./B.S/M.E/M.Tech/M.S in Electrical Engineering, Electronics, Communications, VLSI, Microelectronics or related field.
- 5–10 years of semiconductor industry experience in digital design.
- Proven experience in high-speed digital circuit design using deep-submicron CMOS technologies.
- Experience designing digital circuits for multi-gigabit serial data-link transceivers, DDR, or high-performance memory interfaces.
- Experience with industry-standard EDA tools for design, simulation, and verification.
- Strong background in complex digital system design and verification.
Preferred Qualifications:
- Experience with Industry Standard design tools.
- Experience with multi-gigabit serial data transceivers.
- Exposure to analog/digital control interfaces.
- Knowledge of synthesis, static timing analysis (STA), and signal processing techniques.
- Familiarity with verification methodologies and tools.
Technical Skills:
- RTL design expertise including CDC analysis and linting.
- Strong scripting and automation skills (Python preferred).
- Solid understanding of high-speed, low-power digital design techniques.
- Ability to translate system-level requirements into detailed digital implementations.
- Strong analytical, problem-solving, and debugging skills.
- Effective communication and collaboration abilities.
Visit us at www.kandou.ai and https://www.linkedin.com/company/kandou-ai/
What this role asks for
80% of this description is written for the role. The rest is Kandou AI's standard text, folded away below.
Compared with Kandou AI's other open jobs.
The team: Engineering HIRES STEADILY
This role is one of 15 open in Engineering. 5 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (11 of 15), C (8 of 15), C++ (7 of 15), Embedded Systems (7 of 15), RTOS (5 of 15), CMake (3 of 15), FPGA (3 of 15)
OTHER ROLES ON THIS TEAM
- Customer Platform, SDK & Interoperability Architect - Randa 1.6T AEC Platform posted Oct 12
- Platform Validation Lead / Manager posted Oct 12
- Embedded Software Technical Lead posted Oct 12
- Firmware Lead posted Oct 12
- Software Architect posted Sep 24
- System Firmware Lead (AI Memory Fabrics) – CXL/PCIe Memory fabric controller posted Sep 11
- Internship - AI Engineer posted Sep 9
- Board Product Project Control Coordinator (PCC/ PJE) posted Sep 9
- Analog Layout Engineer (Lead) posted Sep 7
- Internship - Semiconductor Engineering posted Sep 1
- Physical Design Engineers - 2 openings posted Aug 19
- Firmware Engineer Bare Metal posted Aug 19
- Firmware Architect posted Aug 19
- Digital Design Engineer, UK, CH posted Aug 19
From the team and dates on Kandou AI's own job board.
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