CPU Verification Engineer (RISC-V)

The team: CPU Engineering

This role is one of 18 open in CPU Engineering. 14 were posted in the last 30 days.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Python (13 of 18), Perl (7 of 18), Verilog (6 of 18), C++ (5 of 18), VHDL (5 of 18), Embedded Systems (4 of 18), C (3 of 18)

OTHER ROLES ON THIS TEAM

• CPU Micro-architect/RTL Designer (Multiple Locations), Italy posted Oct 8
• CPU Verification Engineer posted Oct 8
• CPU SRAM Design Engineer posted Oct 7
• CPU Post-Silicon Performance Engineer posted Oct 7
• CPU Physical Design CAD Engineer (Sr Staff) posted Oct 6
• CPU Server Physical Design Methodology, Infrastructure and Automation Engineer posted Oct 6
• Senior Software Engineer — RISC-V Instruction Set Simulator posted Oct 2
• Software Engineer — RISC-V Random Test Generator posted Oct 2
• Senior Software Engineer — RISC-V Instruction Set Simulator (Simulator Engineer) posted Oct 2
• CPU Micro-Architecture and RTL Design Engineer (RISC-V) posted Oct 2
• CPU STA CAD Engineer posted Oct 2
• CPU SRAM Design Engineer - Sr Staff / Principal posted Oct 2
• CPU Server Physical Design Engineer, Santa Clara posted Oct 1
• Principal CPU Power Modeling Engineer (San Diego, CA) posted Sep 17
• RISCV CPU System RTL Engineer posted Sep 17
• CPU Integration & 3DIC CAD Engineer posted Sep 17
• CPU Physical Design Engineer (Austin) posted Sep 17

From the team and dates on Qualcomm's own job board.