Physical Design Engineer
San Diego, California, United States of America
- Salary
- $101,400 - $152,200
- Level
- Mid
- Work type
- On-site · San Diego
Not stated in the posting: visa.
Open. First seen 4 November 2026.
About the role
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drive communication and data…
What this role asks for
Particular to this role
Bash · Unix
Rare in Qualcomm's other 299 open postings.
Standard for software engineering roles
Python
Common in software engineering postings at any company.
Compared with Qualcomm's other open jobs.
The team: ASICS Engineering HIRES STEADILY
This role is one of 342 open in ASICS Engineering. 132 were posted in the last 30 days and the oldest in December: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (179 of 342), Verilog (122 of 342), Perl (111 of 342), C++ (95 of 342), C (93 of 342), Embedded Systems (76 of 342), FPGA (64 of 342)
OTHER ROLES ON THIS TEAM
- ASIC Validation Engineer posted Nov 4
- Senior Engineer - Modem System Validation posted Nov 3
- Senior ASIC Validation Engineer posted Nov 3
- Peripherals Design Verification - Staff Engineer posted Nov 3
- Peripherals Design Verification -Sr Engineer posted Nov 3
- Optical Systems Validation Engineer posted Nov 3
- DFT Engineering Director posted Oct 30
- ASIC Design Senior Staff Engineer posted Oct 30
- NoC Interconnect Design Engineer and Architect posted Oct 30
- NoC Interconnect Design Engineer and Architect posted Oct 30
- Pre/Post Silicon Validation Engineer with PMIC Expertise posted Oct 30
- SVE content integration & SKU functional validation engineer posted Oct 30
- ASIC Verification Principal Engineer posted Oct 30
- HW Board Designer - Haifa posted Oct 30
- Physical Design Engineer posted Oct 29
- Physical Design Engineer posted Oct 29
- NOC DV Assoc Engineer posted Oct 29
- Senior Hardware Engineer - SoC Architecture & Design - Qualcomm - Grenoble, France posted Oct 29
- HW IP designer - Qualcomm - Guyancourt or Sophia, France posted Oct 29
- Senior Physical Design Engineer posted Oct 28
- SoC Physical Design Engineer (Lead/Staff) posted Oct 28
- EM Passives and RF Module Design Engineer, Senior posted Oct 28
- SOC Design Verification Sr Lead Engineer posted Oct 28
- Senior Lead Physical Design Engineer posted Oct 28
- SOC Verification and Methodology Engineer posted Oct 28
- Design Verification (NPU) - Sr Lead Engineer posted Oct 28
- RTL Design (SOC) Engineer-Principal/Manager posted Oct 27
- SOC Design Verification Engineer posted Oct 27
- ASICS Design Engineer, Principal posted Oct 27
- Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer posted Oct 27
- Implementation Timing / STA Design Engineer posted Oct 27
- GPU Compiler Engineer - Cambridge, UK posted Oct 27
- Silicon Validation Engineer posted Oct 27
- Staff Engineer - Pre/Post Si validation posted Oct 27
- Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer posted Oct 27
- SOC Implementation Engineer, Lead posted Oct 27
- Verification Engineer, Senior posted Oct 26
- MSIP Design Verification Engineer - Cork, Ireland posted Oct 26
- Principal Engineer posted Oct 26
- HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required) posted Oct 26
- Low Power Design/Methodology Engineer posted Oct 26
- High Speed Validation Engineer, Senior posted Oct 26
- Design Technology posted Oct 26
- DRAM Verification Engineer, Up to Sr. Staff posted Oct 26
- ASIC Design Verification Engineer (Security Group) - Sr Staff posted Oct 23
- System Performance Architect posted Oct 23
- DDR Design Verification Lead Engineer posted Oct 23
- ASICS Design Verification Engineer-Senior to Staff posted Oct 23
- Design Verification - Senior Staff Engineer/Mgr posted Oct 23
- Physical Design Senior Staff Engineer posted Oct 23
- SOC Design Verification Sr Lead Engineer posted Oct 23
- ASICS Design Verification Engineer posted Oct 22
- DFT Engineer posted Oct 22
- ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems posted Oct 22
- Staff Signal Integrity Engineer posted Oct 22
- RTL core/processor Microarchitecture Engineer posted Oct 21
- RTL core/processor Microarchitecture Engineer posted Oct 21
- Camera IP Verification - Sr Lead Engineer posted Oct 21
- VLSI Software Engineer posted Oct 21
- Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France posted Oct 20
- Analog / Mixed-Signal SerDes Design Engineer - Cork, Ireland posted Oct 20
- Senior Software CAD Engineer - Cork, IRL posted Oct 20
- SoC Power Design Engineer posted Oct 20
- (Sr) Staff SOC Architect - AI Accelerators (Multiple Locations) posted Oct 20
- Principal SOC Architect, AI Accelerators (Multiple Locations posted Oct 20
- ASICS Design Engineer, Senior to Staff posted Oct 19
- Physical Design Engineer posted Oct 19
- ASICS Design Verification Engineer-Senior posted Oct 19
- SOC Limits Management Architect posted Oct 19
- ASICS Design Engineer, Senior Staff to Principal Level posted Oct 19
- EVA Design Verification Engineer, Senior - Cork, Ireland posted Oct 16
- PST Validation Engineer posted Oct 16
- SoC Power Validation Engineer posted Oct 16
- SoC Debug Engineer, Senior Staff posted Oct 16
- Design Verification Engineer - Haifa posted Oct 16
- System Validation Lead, Staff (AI Accelerator Platform) posted Oct 16
- DDR Validation Lead, Staff (AI Accelerator Platform) posted Oct 16
- Peripherals (Ethernet) Validation Engineer – Staff/ Sr. Lead / Senior Engineer posted Oct 16
- FPGA Design & Firmware Engineer, Staff posted Oct 16
- FPGA Design & Firmware Engineer, Staff posted Oct 16
- SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform) posted Oct 16
- SoC Debug Engineer, Staff posted Oct 16
- Senior Emulation Performance Methodology & Debug Engineer posted Oct 16
- Emulation Performance/Debug Engineer posted Oct 16
- SoC Infrastructure/NoC, Power & Performance Validation Engineer posted Oct 16
- Sr ASIC Design Verification Engineer, Low Power AI posted Oct 15
- Pre-Silicon Validation Engineer posted Oct 15
- Near-Memory Compute System Validation Engineer posted Oct 15
- System Validation Lead (Premium Mobile Platforms) posted Oct 15
- NOC DV Engineer posted Oct 15
- DSP Micro-Architect RTL Engineer posted Oct 15
- SoC Infrastructure/NoC, Power & Performance Validation Lead, Staff (AI Accelerator Platform) posted Oct 15
- RFIC Circuit Design Engineer, Senior posted Oct 14
- Senior Staff Engineer - Microcontroller Sub-System Design posted Oct 14
- Video IP Design Verification Engineer posted Oct 14
- Principal Advanced Node Technology Yield & Diagnostics Engineer posted Oct 14
- Microcontroller Sub-System Design Engineer/ Staff Engineer posted Oct 14
- SOC Design Engineer posted Oct 13
- AI System Architect (NPU / GPU / Interconnect) posted Oct 13
- Design Verification Engineer — Memory Subsystem (Vancouver) posted Oct 13
- Senior Systems Verification Engineer - Qualcomm - Sophia or Guyancourt, France posted Oct 13
- Design Engineer, Senior Staff/Manager posted Oct 13
- Senior SoC Debug Engineer posted Oct 13
- ASIC Modelling Engineer, Senior - Cork, Ireland posted Oct 12
- Lead Engineer - Pre/Post Si validation posted Oct 9
- SoC Sr Validation Engineer - Power Management posted Oct 9
- Physical Design Engineer, Sr. Staff posted Oct 8
- Emulation Performance Methodology & Debug Engineer posted Oct 8
- Senior Emulation Performance Methodology & Debug Engineer posted Oct 8
- ASICS Design Verification Engineer (Vancouver, Markham OR Remote) posted Oct 8
- Staff Emulation Build Quality, Performance & Debug Engineer posted Oct 8
- Video Design Verification - Sr Engineer posted Oct 8
- Next Gen, High-Speed, Memory and Cache Controller Design Engineer posted Oct 7
- Firmware Engineer, Edge AI Silicon Validation (Embedded C) posted Oct 7
- Front-End Implementation Engineer (Staff) (Timing & Synthesis)- Cork, Ireland posted Oct 7
- Memory Designer posted Oct 7
- ASICS Design Verification Engineer (Multiple Levels) - Vancouver OR Markham posted Oct 7
- Design Engineer - Hod Hasharon posted Oct 7
- SOC Design Verification Engineer posted Oct 7
- Director , Engineering (GPU Physical Design) posted Oct 7
- Hardware Verification, Engineer at Qualcomm Interconnect Technology Center (QITC) - France posted Oct 7
- Next-Gen System Cache ASIC Digital Design Engineer posted Oct 7
- EDA/CAD Software Engineer, Staff posted Oct 7
- Memory Circuit Design Engineer posted Oct 7
- DDRSS Systems Engineer posted Oct 7
- PMIC Design Verification Lead (Sr Staff Engineer) posted Oct 6
- BEOL Process Integration Engineer, up to Sr. Staff posted Oct 6
- SOC Design Verification Engineer posted Oct 6
- SOC Debug Engineer posted Oct 6
- Silicon Validation Senior Engineer posted Oct 6
- High-Bandwidth Memory (HBM) System Validation Lead (AI Accelerator Platform) posted Oct 6
- SOC Design Verification Staff Engineer posted Oct 5
- Camera Frontend Implementation Engineer posted Oct 5
- DFT-Staff Engineer posted Oct 2
- Architecture/System Validation Engineer posted Oct 2
- Physical Design Engineer posted Oct 2
- VLSI Frontend CAD Applications Engineer posted Oct 2
- Foundry Engineer for Advanced Technology (Device/Process/ Product) posted Oct 2
- Physical Design (Multiple levels) posted Oct 2
- Security System Test Engineer posted Oct 1
- Staff Analog IC Design Engineer (ADC) posted Oct 1
- Staff RF Hardware Engineer - Device Technology posted Oct 1
- Physical Design Engineer, Staff - Hod Hasharon posted Oct 1
- Design Verification Engineer - NPU- Engineer to Sr. Staff Engineer posted Oct 1
- SoC Physical Design Engineer (Lead/Staff/Senior Staff) - HM PD team posted Oct 1
- DRAM Circuit Design, Staff posted Oct 1
- Physical Design Engineer, Senior Staff - Hod Hasharon posted Oct 1
- SoC Infrastructure/NoC, Power & Performance Validation Engineer, Staff posted Sep 30
- SOC Clock & Power Management Validation Engineer, Staff posted Sep 30
- DDR Validation Engineer, Staff posted Sep 30
- DDR Validation Engineer posted Sep 30
- VLSI IP Characterization Engineer, Senior to Staff posted Sep 30
- System Validation Engineer (AI Accelerator Platform) posted Sep 30
- SVE Validation framework and QA Engineer posted Sep 30
- DDR PHY Senior Lead Digital Design Engineer posted Sep 30
- AMS Silicon Validation Engineer, Senior posted Sep 30
- Framework Developer Engineer posted Sep 30
- Physical Design Engineer- Staff to Sr. Staff posted Sep 29
- Junior DevOps Engineer – Jenkins - Cork, Ireland posted Sep 28
- Validation Engineer posted Sep 28
- Manager, SoC Systems Validation Engineering (SVE) posted Sep 28
- Security Design Engineer - Cork, IRL posted Sep 28
- SoC Platform Architect - RISC-V posted Sep 28
- Senior Test Automation Engineer (Python) - Cork, Ireland posted Sep 28
- Mixed-Signal IP Memory & Die-to-Die (D2D) System Engineer - Cork, Ireland posted Sep 28
- FPGA Emulation Engineer (Staff/ Senior Staff/ Principal) posted Sep 28
- Processor ASIC RTL Design Engineer posted Sep 28
- SOC Verification Principal Engineer posted Sep 28
- Staff Verification Engineer, Compute Subsystems posted Sep 25
- ASIC Design Engineer posted Sep 25
- Hardware Verification Engineer - Cork, Ireland posted Sep 25
- Senior Staff Hardware Verification Engineer - Cork, Ireland posted Sep 25
- NPU Synthesis Engineer, Principal posted Sep 25
- NPU AI/Processor Synthesis Engineer- Sr Staff posted Sep 25
- SoC Design and Integration Engineer posted Sep 25
- Senior Hardware Verification Engineer - Cork, Ireland posted Sep 25
- NPU AI/Processor Synthesis Engineer- Sr Staff posted Sep 25
- Physical Design Engineer, Staff posted Sep 25
- Analog / Mixed-Signal IP DDR Design Senior Engineer - Cork, Ireland posted Sep 24
- Physical Design Engineer, Staff posted Sep 24
- Senior Staff Hardware Engineer - Hod Hasharon posted Sep 24
- Senior Performance Engineer posted Sep 23
- GSoC Design Verification Engineer posted Sep 23
- Senior Director, Project Engineering - Taiwan posted Sep 23
- SOC Power Architect posted Sep 23
- Data Center SoC Power & Limits Architect posted Sep 23
- Senior Physical Design Engineer posted Sep 22
- Physical Design Staff Engineer posted Sep 22
- Emulation Engineer - Sr/Lead/Staff Engineer posted Sep 22
- Senior Staff Physical Design Engineer posted Sep 22
- Senior Lead Physical Design Engineer posted Sep 22
- Senior Lead Physical design Engineer posted Sep 22
- STA Staff Engineer posted Sep 22
- SOC Power/Limits Architect posted Sep 22
- System Hardware Validation Engineer (All Levels) - Cork, Ireland posted Sep 22
- Senior Lead STA Engineer posted Sep 22
- Physical Design Engineer posted Sep 22
- Physical Design Engineer posted Sep 22
- SoC Systems & Infrastructure Engineer (Design • Validation • Debug • FPGA • Emulation • Software) posted Sep 22
- Senior STA Engineer posted Sep 22
- Post Silicon Validation -Sr/Lead/Staff Engineer posted Sep 22
- Systems/SOC Architecture, Senior to Staff posted Sep 21
- Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer ( posted Sep 21
- PDK/CAD Design Automation Engineer posted Sep 20
- Staff Mixed-Signal Digital Design Engineer - Cork, Ireland posted Sep 18
- High Performance DSP core Implementation(Synthesis) Engineer posted Sep 18
- SOC RTL Design Engineer - Staff posted Sep 18
- High Performance DSP core Implementation(Synthesis) Senior Engineer posted Sep 18
- DFT Staff Engineer posted Sep 18
- Senior Power Engineer posted Sep 18
- High Performance DSP core Implementation(Synthesis) Staff Engineer posted Sep 18
- High Performance DSP core Implementation(Synthesis) Senior Lead Engineer posted Sep 18
- Power Engineer posted Sep 18
- Senior Staff RF/Analogue IC CAD Engineer - Farnborough, Qualcomm posted Sep 18
- Senior Staff Engineer, Diagnostics and AI posted Sep 18
- Staff Engineer- Power Engineer posted Sep 18
- Memory Designer posted Sep 17
- ASIC Design Verification Engineer (Santa Clara, CA) posted Sep 17
- SOC Design Verification Engineer – Data Center Solutions posted Sep 17
- Physical Design Engineer (Engineer up to Principal Level) posted Sep 17
- Microprocessor Silicon Validation and Optimization Engineer-Staff posted Sep 17
- Principal Ethernet Scale-Out Architect, AI Data Center posted Sep 17
- System Performance Modeling Engineer posted Sep 17
- EDA/CAD SW Engineer (Multiple Levels) posted Sep 17
- Server SoC Security Architect posted Sep 17
- SOC Verification and Methodology Engineer -Staff posted Sep 17
- Synthesis-DFT Stitch CAD Engineer posted Sep 17
- ASIC/RTL Design Engineer for High-speed Interfaces posted Sep 17
- Engineer-Staff posted Sep 17
- Staff CPU/NPU Architecture RTL Design Engineer posted Sep 17
- Always On Subsystem Power Management Firmware Engineer to Always On Subsystem Power Management Firmware Engineer posted Sep 17
- VLSI Design Engineer for Server / Data Center Products posted Sep 17
- Foundry Engineer for Advanced Technology, Sr. Staff posted Sep 17
- FPGA Firmware Engineer / FPGA Design Engineer posted Sep 17
- CAD Engineer on ML/AI for Design Verification posted Sep 17
- CPU Physical Design Engineer, Senior to Senior Staff Level posted Sep 17
- VLSI Design Engineer for Server / Data Center Products posted Sep 17
- ASIC Design Verification Engineer (Santa Clara, CA) posted Sep 17
- RTL Feasibility Engineer, AI/ML Processors posted Sep 17
- SOC Design Verification Engineer-Staff posted Sep 17
- Senior ASIC Design Engineer, Compute DSP/AI Processors (multiple levels) posted Sep 17
- Senior ASIC Design Verification Engineer, Compute DSP/AI Processors (multiple levels) posted Sep 17
- FPGA Firmware Engineer / FPGA Design Engineer posted Sep 17
- Staff ASIC Verification Engineer, Low Power AI posted Sep 17
- Verification Hardware Engineer posted Sep 17
- Connectivity Project Engineer, Principal posted Sep 17
- Connectivity Project Engineer, Principal posted Sep 17
- ASIC DTCO, Timing and Technology Engineer posted Sep 17
- Sr. Staff/Principal PCIE Subsystem Architect posted Sep 17
- SOC Design Verification Engineer-Staff posted Sep 17
- SOC Design Verification Engineer posted Sep 17
- Staff Engineer, Physical Design/Implementation posted Sep 17
- Engineer posted Sep 17
- Digital Design Verification Engineer, Staff posted Sep 17
- SoC Modeling Engineer posted Sep 17
- SOC Verification and Methodology Engineer posted Sep 17
- Staff SOC Physical Design Engineer posted Sep 17
- DDRSS Validation Engineer (RTL + Silicon Debug) posted Sep 17
- Senior Digital Design CAD Engineer posted Sep 17
- Senior Director SoC Architecture - AI Accelerators (Multiple Locations) posted Sep 17
- SOC Design Verification Engineer-Staff posted Sep 17
- Memory Control Design Engineer posted Sep 17
- Physical Design Engineer, Staff posted Sep 17
- ASIC Methodology Engineer posted Sep 17
- Physical Design Engineer - DSP Team posted Sep 17
- Design Engineer (Low Power) posted Sep 17
- AI Systems Hardware Engineer posted Sep 17
- ASIC Design Engineer (Hardware Security) posted Sep 17
- Staff GPU Engineer posted Sep 17
- Senior SOC Physical Design Engineer posted Sep 17
- Next-Gen, High-Speed Memory Subsystem ASIC Digital Design Engineer posted Sep 17
- Staff Memory Controller Architecture and Design Engineer posted Sep 17
- ASICS Design Verification Engineer-Senior posted Sep 17
- Design Verification Engineer — Memory Subsystem posted Sep 17
- Hardware System Design Engineer, Senior or Staff posted Sep 17
- 3D Memory Chip Architect and Design, Principal Engineer posted Sep 17
- Computer/Data Science Staff Engineer for CAD - Cork, Ireland posted Sep 16
- Computer Science Senior Engineer for CAD - Cork, Ireland posted Sep 16
- Senior Mixed-Signal Physical Design Engineer - Cork, Ireland posted Sep 15
- Physical Design Engineer, Senior/Staff - Cork, Ireland posted Sep 15
- Camera VI Engineer posted Sep 15
- Agentic AI Developer, Senior - Cork, Ireland posted Sep 15
- Security HW Design Verification Engineer, Senior - Cork, Ireland posted Sep 14
- VLSI Software Engineer posted Sep 11
- ASIC / NoC Power and Solutions Senior/Staff Engineer - Qualcomm - Guyancourt, France posted Sep 11
- Staff design Verification Engineer posted Sep 11
- ASIC / NoC Verification & Solutions Engineer- Qualcomm - Guyancourt, France posted Sep 11
- Staff Test Automation Engineer (Python) - Cork, Ireland posted Sep 8
- AI Engineering & Methodology Architect - Cork, Ireland posted Sep 8
- Formal Verification Senior Engineer - Qualcomm, Cambridge, UK posted Sep 4
- Test Engineer, Senior - Hod Hasharon posted Sep 2
- Power Integrity Design Engineer – PDN / EMIR - Cork, Ireland posted Sep 2
- Physical Design Staff Engineer - Cork, Ireland posted Sep 1
- ASIC Design Verification Engineer, up to Sr. Staff posted Aug 31
- Linux Platform & HLOS Stack Developer, Senior/Staff - Cork, Ireland posted Aug 31
- Pre-Silicon Verification Engineer - Hod Hasharon posted Aug 27
- ASIC Design Engineering - Multiple function posted Aug 24
- FPGA Emulation Engineer, up to Staff posted Aug 21
- ISP Design Engineer, up to Staff posted Aug 21
- CPU Post Silicon Power and Performance Engineer, Senior/Staff - Cork, Ireland posted Aug 20
- Data Converters Mixed Signal Lead, Sr. Staff posted Aug 18
- CPU Competitive Analysis Engineer, Entry Level up to Staff posted Aug 13
- SOC Design Verification Engineer– Pre-Si/Post-Si Verification posted Aug 10
- Senior Design Verification Engineer- Haifa, Hod Hasharon, Ramat Gan posted Aug 4
- Video Codec Design Engineer, up to Staff posted Jul 31
- Software Engineer - Qualcomm - Guyancourt, France posted Jul 23
- NoC Verification Engineer - Qualcomm - Guyancourt, France posted Jul 23
- Microcontroller Sub-System Verification Engineer / Senior Engineer, - Cork, Ireland posted Jul 22
- Hardware Verification Senior/Staff/Senior Staff Engineer at Qualcomm Interconnect Technology Center (QITC) posted Jul 22
- Senior HW IP designer - Qualcomm - Guyancourt, France posted Jul 22
- Staff / Senior Staff Engineer - ASIC / NoC SoC deployment architect - Qualcomm - Guyancourt, France posted Jul 21
- Video Codec Digital Circuit Design Engineer posted Jul 21
- SOC Design Verification Engineer– Pre-Si/Post-Si Verification posted Jul 20
- Architecture Engineer, Senior Staff - Hod HaSharon posted Jul 20
- SOC Design Verification Engineer, Staff– Pre-Si/Post-Si Verification posted Jul 20
- MBIST Diagnostics Engineer, up to Sr. Staff posted Jul 19
- Standard Cell Layout Engineer posted Jul 16
- Yield Diagnostics Engineer, up to staff posted Jul 16
- CPU Design Verification Engineer, Staff/ Sr Staff (RISC V) - Cork, Ireland posted Jul 13
- 3DIC Yield Analytics & Diagnostics Engineer, Staff posted Jul 10
- Advanced Node Process and Yield Diagnostics Engineer, Staff posted Jul 10
- SoC Design and Integration Engineer posted Jul 8
- Validation Engineer posted Jul 6
- Software Engineer - Qualcomm - Guyancourt, France posted Jul 2
- ASIC DV Engineer, Principal/Mgr posted Jul 1
- SoC Design & Synthesis Engineer posted Jun 29
- SOC Power Design Engineer posted Jun 29
- Analog / Mixed-Signal PLL Design Engineer, Senior - Cork, Ireland posted Jun 11
- Senior Staff Engineer in Microcontroller Sub-System Verification- Cork, Ireland posted Jun 10
- CPU Microarchitect/RTL design Engineer, Senior/Staff - Cork, Ireland posted Jun 5
- System Validation Engineer, Senior posted May 21
- CPU Physical Design Engineer - Cork, Ireland posted May 20
- IP Library Circuit Design Engineer posted May 20
- Sr QA Compiler posted May 7
- STA Design Engineer - Static Timing Analysis - Cork, Ireland posted May 6
- DRAM Circuit Designer, up to Staff posted Apr 13
- Staff Mixed Signal IC Design Engineer posted Apr 9
- High‑Speed IP Integration Engineer, Up to Snr Staff (USB/PCIe/UHS) (Hsinchu, Taipei) posted Mar 20
- CPU RTL Design Engineer posted Mar 17
- CPU Design Verification Engineer - Cork, Ireland posted Jan 27
- DRAM PHY Designer, up to Staff posted Dec 30
From the team and dates on Qualcomm's own job board.
Other openings for this role
2 open postings for this role in San Diego, California, United States of America, first posted 27 October 2026. The company is likely hiring for more than one position. None has been taken down and posted again.
- 4 November 2026 – open (this posting)
- 27 October 2026 – open
Salary context
12 other open postings titled Physical Design Engineer state a salary: median USD 180,000 to USD 290,000 a year.
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