Cadence
Lead Design Engineer
Pune, India
- Level
- Lead
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 3++ Year ASIC Design / Verification experience. Required Expertise in PCIe / Storage (ONFI, XSPI, SD/eMMC) Design and Verification domain. Good debug skills and good…
Other openings for this role
4 open postings for this role in Pune, India, first posted 14 March 2026. The company is likely hiring for more than one position. None has been taken down and posted again.
- 2 October 2026 – open (this posting)
- 2 October 2026 – open
- 2 October 2026 – open
- 14 March 2026 – open
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