Post-Silicon Validation Engineer

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities

Perform hands-on post-silicon validation

• Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
• Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
• Drive complex issues from initial failure through root-cause analysis and final resolution.
• Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
• Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
• Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.

Develop automation to improve validation coverage, debug efficiency, and regression testing.

Required Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 5+ years of engineering experience in silicon validation, post-silicon debug, or high-speed interface development.
• Strong hands-on knowledge of PCIe architecture and protocol.

Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.

• Strong problem-solving skills and ability to independently drive issues to root cause.
• Experience working across hardware, firmware, and software boundaries.

Good scripting/programming skills, preferably Python

• Good Linux knowledge and experience with Linux PCIe debug tools.
• Strong communication and collaboration skills.

Preferred Qualifications

Experience with PCIe Gen4/Gen5/Gen6/Gen7

• Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.
• Experience with PCIe compliance and interoperability testing.
• Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.

Experience with PCIe switches, or networking/accelerator platforms.

Practical experience using AI/ML tools for engineering debug and automation.