Principal Product Engineer
- Salary
- $00 - $240,000
- Level
- Principal
Not stated in the posting: work type, visa.
Open. First seen 2 October 2026.
About the role
Astera Labs's standard text
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Overview:
We are seeking an experienced and hands-on Principal Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives.
Basic Qualifications:
- Minimum of 8 years of experience in the field of post silicon product development dealing with high-speed I/O (product test or validation)
- Have gone through at least one cycle of full product development life cycle
- Strong academic/technical background in electrical or computer engineering; Bachelor’s is required; MS preferred
- Strong problem-solving skills that involve system level analysis with test hardware, test program and DUT.
- Digital and analog circuit level understanding for DUT
- Excellent team player with great communication skills
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks
Required Experience:
- Hands on experience with using the Advantest 93k ATE platform with specific skills updating ATE test programs for wafer sort and final test solutions or similar ATE platform
- Detailed mindset monitoring device ATE test yields, ATE test time, device quality and rolling out new ATE test programs using consistent BKMs
- Strong data analysis skills using tools such as JMP or Spotfire calculating limits and drawing conclusions
- Energetic work mindset meeting the demands of shipping quality parts to Astera Labs’ customers through the manufacturing stage of development
- Hands on experience in product/package qualification
Preferred Experience:
- Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above), etc. and/or memory interfaces such as (LP)DDR5/4
- Working with silicon validation teams to ensure device performance meets production requirements
- Firmware development in C/C++, scripting in Python, or other equivalent programming experience
The base salary range is USD 185,00 - USD 240,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Astera Labs's standard text
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
What this role asks for
Standard for software engineering roles
Python
Common in software engineering postings at any company.
72% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.
Read against Astera Labs's other open postings on this site.
The team: ASIC Engineering HIRES STEADILY
This role is one of 53 open in ASIC Engineering. 13 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (36 of 53), Verilog (21 of 53), Embedded Systems (20 of 53), Perl (14 of 53), C (9 of 53), C++ (8 of 53), FPGA (5 of 53)
OTHER ROLES ON THIS TEAM
- Principal Digital Design Engineer posted Oct 14
- Principal Physical Design Engineer posted Oct 12
- Principal Physical Design CAD Engineer posted Oct 11
- Principal Digital Design Engineer posted Oct 5
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Senior System Validation Engineer posted Sep 16
- Digital Design Manager posted Sep 15
- Principal Digital Design Engineer posted Sep 14
- Manager Design Verification posted Sep 14
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Senior ATE Test Engineer posted Aug 31
- Manager, ATE Test Engineering posted Aug 28
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Physical Design Engineer, Methodology posted Jul 22
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- Soc Design Verification Director posted Jun 24
- Principal DFT Engineer posted Jun 8
- Staff DFT Engineer posted Jun 8
- Staff Physical Design Engineer - SoC EMIR Engineer posted Jun 7
- Physical Design Student posted Jun 2
- Staff/ Principal Design Verification Engineer posted Jun 1
- Senior Design Verification Engineer posted Jun 1
- Principal Physical Design Engineer, STA posted May 20
- Manager, Package Design Engineering posted Mar 26
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- Principal ATE Test Engineer posted Dec 19
- Technical Chief of Staff for ASIC Engineering posted Nov 20
- Principal Emulation Engineer posted Sep 9
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
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