Principal Digital Design Engineer
- Salary
- $185,000
- Level
- Principal
Not stated in the posting: work type, visa.
Open. First seen 6 October 2026.
About the role
Astera Labs's standard text
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description
We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.
Basic Qualifications:
- Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
- +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
- Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
- Authorized to work in the US and start immediately.
Required Experience:
- Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
- Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
- Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
- Experience with Synopsys and/or Cadence digital design tools/flows
- Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
- Familiarity with UVM based design verification
- Silicon bring-up and debug expertise
- Small-geometry CMOS (≤28nm) design
Preferred Experience:
- Firmware development with C-language, scripting with Python or other equivalent programming languages.
- Development/support for PCIe or Ethernet Switch products.
The base salary range is $185,000.00 USD – $240,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
Astera Labs's standard text
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
What this role asks for
Standard for software engineering roles
Python
Common in software engineering postings at any company.
67% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.
Read against Astera Labs's other open postings on this site.
The team: ASIC Engineering HIRES STEADILY
This role is one of 53 open in ASIC Engineering. 13 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (36 of 53), Verilog (21 of 53), Embedded Systems (20 of 53), Perl (14 of 53), C (9 of 53), C++ (8 of 53), FPGA (5 of 53)
OTHER ROLES ON THIS TEAM
- Principal Digital Design Engineer posted Oct 14
- Principal Physical Design Engineer posted Oct 12
- Principal Physical Design CAD Engineer posted Oct 11
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Senior System Validation Engineer posted Sep 16
- Digital Design Manager posted Sep 15
- Principal Digital Design Engineer posted Sep 14
- Manager Design Verification posted Sep 14
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Senior ATE Test Engineer posted Aug 31
- Manager, ATE Test Engineering posted Aug 28
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Physical Design Engineer, Methodology posted Jul 22
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- Soc Design Verification Director posted Jun 24
- Principal DFT Engineer posted Jun 8
- Staff DFT Engineer posted Jun 8
- Staff Physical Design Engineer - SoC EMIR Engineer posted Jun 7
- Physical Design Student posted Jun 2
- Staff/ Principal Design Verification Engineer posted Jun 1
- Senior Design Verification Engineer posted Jun 1
- Principal Physical Design Engineer, STA posted May 20
- Principal Product Engineer posted Apr 1
- Manager, Package Design Engineering posted Mar 26
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- Principal ATE Test Engineer posted Dec 19
- Technical Chief of Staff for ASIC Engineering posted Nov 20
- Principal Emulation Engineer posted Sep 9
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
Other openings for this role
4 open postings for this role in San Jose, California, United States, first posted 2 October 2026. The company is likely hiring for more than one position. None has been taken down and posted again.
- 14 October 2026 – open
- 6 October 2026 – open (this posting)
- 2 October 2026 – open
- 2 October 2026 – open
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