CPU Digital Design Engineer
- Level
- Mid
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
Job Description:
Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in:
- Perform CPU development and design integration for CPU subsystem.
- Micro-architecture and design of RISC based CPU.
- Explore latest technologies in processor for 5G application.
Minimum Qualifications:
- Master Degree in Electrical Engineering, Computer Science or Computer Engineering.
- At least 3 years of CPU related Architect/RTL/Verification/Implementation design experience
- Knowledge and practical experience with common RISC CPU architecture.
- Ability to bring design concept to successful silicon
Preferred Qualifications:
- PhD in Electrical Engineering, Computer Science or Computer Engineering is a PLUS.
- 5+ years of CPU related Architect/RTL/Verification/Implementation design experience
- Familiarity with CPU architecture knowledge and micro-architecture knowledge
- Familiarity with chip digital design flow, including RTL integration, simulation, STA, clock tree, or low power design
- Familiarity with Symmetric Multi-threading (SMT), ARM/MIPS CPUs, or RISC-V.
- Familiarity with Symmetric Multi-processing (SMP) and Snoop-based multi-processor architecture.
- Cross-site working experience is a PLUS.
- Experience with Foundry, Post-Silicon, FPGA, DVT, SLT debug is a PLUS.
Baidu USA's standard text
#LI-DNI
What this role asks for
Particular to this role
FPGA
Rare in Baidu USA's other 14 open postings.
99% of this description is written for the role. The rest is Baidu USA's standard text, folded away below.
Read against Baidu USA's other open postings on this site.
The team: XingYun Research & Development Center
This role is one of 11 open in XingYun Research & Development Center.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
C++ (6 of 11), C (4 of 11), Perl (4 of 11), Python (4 of 11), Deep Learning (2 of 11), FPGA (2 of 11), Machine Learning (2 of 11)
OTHER ROLES ON THIS TEAM
- Senior RTL Design Engineer posted Aug 22
- CPU Design Architect / Principal Digital Design Engineer posted Aug 22
- System Software Engineer – Lead Engineer posted Aug 14
- Design Verification Engineer posted Jun 18
- SoC System Hardware Architect posted Jun 18
- SoC Memory Subsystem Architect posted Jun 18
- Low Power SoC Hardware Architect posted Jun 18
- Machine Learning System Software Architect posted Jun 16
- Machine Learning System Hardware Architect posted Jun 15
- CPU/GPU/Processor Hardware Architect posted Jun 15
From the team and dates on Baidu USA's own job board.
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