SoC Memory Subsystem Architect

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?

We’re looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.

Description

We are looking for a world-class Memory Subsystem Architect to join our SoC team at Baidu’s Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment. Your job responsibilities as a Memory Subsystem Architect will be providing technical leadership through all phases of Baidu’s AI SoC development, but primarily focused on unified memory space architecture design for Baidu AI accelerator SoC. The working goal is to build unified memory space for thousands of accelerators from user's perspective.

Developing architecture and micro-architecture to improve the state-of-the-art AI SoC memory system. Explore and evaluate the architectural design choices in SoC fabrics, system caches, system coherency, and MMUs.

Work with software and SoC design team to define architecture and build unified memory space system across distributed AI training system.

Work with Hardware design, verification, emulation, and validation teams to build and test the hardware architecture, performance and functionality.

Participate in performance simulation of features to improve memory subsystem efficiency. Analyzing benchmarks, application workloads and performance simulation results to identify areas for microarchitecture optimizations.

Debug performance and functional issues with high-level models, RTL simulation, and silicon.

Qualifications

• 10+ years of experience in Silicon architecture or IP design mainly focusing on memory subsystem.
• Strong understanding of distributed AI training system's requirement on SoC memory subsystem.
• Demonstrated experience in HW digital design and understanding of CPU/HW Accelerators and/or Peripheral design.
• Familiarity with SW and Operating system practices and requirements on memory system.
• Experience in System Performance analysis and debug in pre and/or Post-Silicon environments.
• Solid background of System interconnect, System MMUs, Caches and Memory Technologies (e.g. HBM, GDDR, DDR and LPDDR4/5).
• Experience with data analysis using Excel, Perl, Python etc.
• Master or PhD in Electrical or Computer Engineering.
• Excellent communication skills in both English and Chinese.