Low Power SoC Hardware Architect

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?

We’re looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.

Description

As a Low Power SoC Architect, you will have the opportunity to independently design and define the lower power subsystem and improve the power efficiency of AI engine, in both data center and edge SoC. You will collaborate with experienced designers, RTL engineers, system and software team, to explore feasibility of ideas, proof of concept and power performance improvement.

Qualifications

• Experience and knowledge of lower power soc architecture and deep expertise in lower power subsystem, power efficient design.
• Lead and drive lower power & most efficient BW to power SoC design, including arch features, RTL changes for low power design, topologies with floorplan/layout and other design aspects
• Work with IPs architects to drive low power design, methodologies, techniques, and features.
• Drive SoC level power convergence by using existing modeling tools and techniques, and developing new state of the art tools, flows, and methodologies.
• Experience and proof of track in power optimization: perf@watt and perf/sq.mm modeling or analysis, is a plus
• Good teamwork with communications and support to solve all levels of architecture definition from micro-architecture to system level to software architecture.
• Proficiency in C/C++ and scripting languages such as Perl or Python.
• Self-driven and leadership skills.
• Knowledge or experience in automotive industry is a plus.
• MS or PhD in Electrical or Computer Engineering.
• Excellent communication skills in both English and Chinese.