Physical Design Engineer - Block Level, Subsystem Implementation
- Salary
- $200K - $375K
- Level
- Senior
- Work type
- On-site · Austin
Not stated in the posting: visa.
Open. First seen 6 November 2026.
About the role
Etched's standard text
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
Etched is building a new category of AI hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level implementation from synthesis through GDSII sign-off. You will drive Block-level & Subsystem PPA Optimization, and collaborate closely with RTL designers to provide actionable feedback, ensuring we iterate at unprecedented speeds to bring our products to market.
Key Responsibilities
- Own block-level and/or subsystem physical design end to end, including floorplanning, synthesis, placement, clock tree synthesis, and routing through GDSII.
- Drive block-level timing closure across all corners and modes, including constraint development, STA debug, and functional and timing ECO implementation.
- Close block-level signoff across EM, IR drop, RC extraction and correlation, and physical verification (DRC, LVS, antenna).
- Generate abstracts, views, and timing budgets for clean hierarchical integration of your blocks into the top level.
- Collaborate with RTL Designers and provide Physical Design feedback to improve PPA.
- Continuously improve the PPA of owned blocks and contribute learnings back into the shared RTL-to-GDSII flow.
- Supervise physical design work outsourced to 3rd party services and be accountable for the quality and closure of delivered blocks.
You may be a good fit if you have
- 5-10+ years of previous experience with PD
- Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
- Experience with back-end design and timing closure on advanced process nodes (5nm and below)
- Experience with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) automated RTL-to-GDSII flows
- Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
- Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis
- Scripting ability in Tcl, Python, or Perl for flow automation and debug
- Deeply creative and able to think from first principles
Strong candidates may also have experience with
- Familiarity with modern ML and LLM model architectures
- Ability to program with Python or another scripting language
- Familiarity with AI tools for programming/coding
- Startup experience or comfort working in fast-paced environments
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification
How we’re different
Etched's standard text
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.
We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.
What this role asks for
Particular to this role
Machine Learning · Perl
Rare in Etched's other 183 open postings.
Standard for software engineering roles
Python
Common in software engineering postings at any company.
84% of this description is written for the role. The rest is Etched's standard text, folded away below.
Compared with Etched's other open jobs.
The team: ASIC
This role is one of 36 open in ASIC.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (30 of 36), Machine Learning (16 of 36), Verilog (16 of 36), LLM (14 of 36), Perl (12 of 36), C (4 of 36), Embedded Systems (4 of 36)
OTHER ROLES ON THIS TEAM
- Silicon Validation Engineer, Software posted Sep 3
- Silicon Validation Engineer, Software posted Sep 3
- Physical Design Engineer - Block Level, Subsystem Implementation posted Jul 30
- Physical Design Engineer - Full Chip Implementation posted Jul 23
- Physical Design Engineer - Full Chip Implementation posted Jul 23
- Physical Design Engineer - Flow & Methodologies posted Jul 23
- Physical Design Engineer - Flow & Methodologies posted Jul 23
- Physical Design Engineer - Block Level, Subsystem Implementation posted Jul 23
- Physical Design Engineer - Block Level, Subsystem Implementation posted Jul 23
- Product Engineer, Silicon Validation posted May 6
- Product Engineer, Silicon Validation posted May 6
- ASIC Technical Program Manager posted May 1
- ASIC Technical Program Manager posted May 1
- Physical Design Engineer posted Apr 16
- Physical Design Engineer posted Apr 16
- Design Verification Engineer - SoC posted Apr 16
- Design Verification Engineer - SoC posted Apr 16
- Design Verification Engineer - Internal IP posted Apr 16
- Design Verification Engineer - Internal IP posted Apr 16
- Design Verification Engineer - Interface IP posted Apr 16
- Design Verification Engineer - Interface IP posted Apr 16
- DFT (Design For Test) Engineer posted Feb 28
- DFT (Design For Test) Engineer posted Feb 28
- Post-Silicon Validation Engineer posted Oct 13
- Post-Silicon Validation Engineer posted Oct 13
- Design Verification Engineer - Interface IP posted Sep 11
- Design Verification Engineer - Interface IP posted Sep 11
- Design Verification Engineer - SoC posted Sep 11
- Design Verification Engineer - SoC posted Sep 11
- Physical Design Engineer posted Aug 11
- Physical Design Engineer posted Aug 11
- RTL Design Engineer posted Jun 11
- RTL Design Engineer posted Jun 11
- Design Verification Engineer - Internal IP posted Jun 11
- Design Verification Engineer - Internal IP posted Jun 11
From the team and dates on Etched's own job board.
Other openings for this role
2 open postings for this role in Austin, first posted 2 October 2026. The company is likely hiring for more than one position. None has been taken down and posted again.
- 6 November 2026 – open (this posting)
- 2 October 2026 – open
Similar jobs
- Sr FPGA Design Engineer (NetSec) at Palo Alto Networks
Shares 4 skills: Perl, LLM, Machine Learning… · Senior level · same country - AI/ML Logic Design Engineer-Senior at Qualcomm
Shares 3 skills: Perl, Machine Learning, Python · Senior level · same city - Senior Silicon Design Verification Engineer at Microsoft
Shares 2 skills: Perl, Python · Senior level · same country - Experienced QA Engineer with Hands-on Automation and AI Skills at Deloitte
Shares 4 skills: Perl, LLM, Machine Learning… · same country - Senior or Staff Design Verification Engineer at Powerlattice Technologies
Shares 2 skills: Perl, Python · same country - Infrastructure Engineering & Projects Intern at Etched
Also at this company
More jobs like this
Is this your posting? Email info@careerholo.com to have it removed.