Product Technical Chip Lead, Senior Director
- Salary
- $260,000 - $295,000
- Level
- Lead
Not stated in the posting: work type, visa.
Open. First seen 2 October 2026.
About the role
Astera Labs's standard text
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle.
As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers.
Location - San Jose, CA OR Israel
Key Responsibilities
- Product Technical Ownership
- Own the full technical lifecycle of the product line—architecture assumptions, design integration, validation strategy, readiness, and customer enablement
- Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and tapeout milestones are met
- Lead development of large-scale chips (300-400mm²) utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures
- Reduce ambiguity by translating product requirements into clear priorities, tradeoffs, and execution paths
- Own the Chip Tapeout and Chip signoff with full responsibility on Chip Quality.
- Cross-Functional Technical Leadership
- Anticipate challenges early, drive alignment across all engineering functions, ensuring risks, dependencies, and decisions are surfaced and resolved at the earliest
- Partner with design verification teams to define coverage goals, regression strategies, and sign-off criteria
- Collaborate with DFT teams on test architecture, scan insertion, BIST, and manufacturing test strategies
- Work closely with physical design teams on timing closure, power optimization, and backend execution
- Process Excellence & Organizational Development
- Establish and reinforce scalable processes, documentation, and handoffs that support company growth
- Provide structured, data-driven decision-making and maintain a crisp operational cadence across the product line
- Transform conflicts to foster a culture of ownership over ego, mentoring and elevating teams while strengthening technical judgment, accountability, and cross-functional collaboration
- Model steady, calm leadership, particularly in high-stakes or ambiguous situations
- Shape engineering culture and talent strategy to support Astera's rapid growth trajectory
Basic Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience across architecture, silicon design, validation, systems, or related domains
- Proven track record of developing large-scale chips (300mm²+) through successful tapeout
- Hands-on experience with 2.5D and 3D advanced packaging technologies and chiplet-based architectures
- Strong understanding of RTL design, design verification, DFT, and physical design flows
- Experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures
- Demonstrated executive leadership of cross-functional technical programs with end-to-end product cycle ownership
- Strong communication and executive presence with the ability to influence at all levels of the organization
Preferred Qualifications
- Master's degree in Electrical Engineering or Computer Engineering
- Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, or Ethernet switching architectures
- Experience with advanced process nodes (7nm, 5nm, or below)
- Background in power management, clocking architectures, or high-speed analog integration
- Experience operating in fast-growing startups or hyper-scale environments
Key Leadership Competencies
- Systems Thinking: See the big picture while managing details
- Emotional Intelligence: Calm under pressure, empathetic, and influential
- Adaptability: Thrive in ambiguity and fast-changing environments
- Execution Discipline: Deliver predictable results without sacrificing innovation
Base salary range is $260,000 to $295,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
Astera Labs's standard text
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
What this role asks for
81% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.
Compared with Astera Labs's other open jobs.
The team: ASIC Engineering HIRES STEADILY
This role is one of 47 open in ASIC Engineering. 15 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (29 of 47), Embedded Systems (22 of 47), Verilog (17 of 47), Perl (12 of 47), C (7 of 47), C++ (6 of 47), FPGA (4 of 47)
OTHER ROLES ON THIS TEAM
- Physical Design Team Lead posted Oct 25
- Physical Design Engineering Director posted Oct 24
- Principal Physical Design Engineer posted Oct 22
- Firmware Engineer posted Oct 20
- Principal Digital Design Engineer posted Oct 14
- Principal Physical Design Engineer posted Oct 12
- Principal Physical Design CAD Engineer posted Oct 11
- Principal Digital Design Engineer posted Oct 5
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Senior System Validation Engineer posted Sep 16
- Digital Design Manager posted Sep 15
- Principal Digital Design Engineer posted Sep 14
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Senior ATE Test Engineer posted Aug 31
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- Soc Design Verification Director posted Jun 24
- Principal Architect posted Jun 9
- Physical Design Student posted Jun 2
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- Expert IC Package Design Lead posted Feb 22
- Technical Chief of Staff for ASIC Engineering posted Nov 20
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
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