Firmware Engineer
- Level
- Mid
Not stated in the posting: salary, work type, visa.
Open. First seen 20 October 2026.
About the role
Astera Labs's standard text
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Job Description:
The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs’ SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs’ products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the customer's needs are fully comprehended.
Basic qualifications:
- Strong academic and technical background in electrical engineering. At a minimum, a Bachelor’s in EE or Computer Science is required.
- Minimum 5 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
- Experience developing firmware to execute with on-chip microcontrollers and C-language software development kits (SDKs) to execute on system host CPUs and embedded microprocessors.
- Experience working with logic designers to implement and test HW-SW interfaces on complex SoCs.
- Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and to work with minimal guidance and supervision.
- Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind!
- Can start immediately.
Required experience:
- High level of proficiency in C (preferred) or C++, including development of C-based SDKs and firmware.
- Proficient in Python for scripting.
- Ability to design, implement, and write unit-level tests.
- Working knowledge of software build environments, gcc/make.
- Experience with developer workflows, SCM (preferably git), code reviews, CI.
- Hands-on experience with Server, Storage, and/or Networking equipment.
- Familiarity with SoC interfaces to various HW blocks, on-chip memory interfaces, and other similar interfaces that are common to chip design.
Preferred experience:
- Firmware development experience using RTOS.
- Experience developing boot-ROM and familiarity working in pre-Silicon environments (Simulation and emulation).
- Experience with secure boot flows (authentication, attestation & standards like DICE, Caliptra) is an asset.
Astera Labs's standard text
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
What this role asks for
Particular to this role
Git · RTOS
Rare in Astera Labs's other 153 open postings.
Standard for embedded / hardware roles
C · C++ · Embedded Systems
Common in embedded / hardware postings at any company.
In most of Astera Labs's ads
Python
Named in most of its open postings, whatever the role.
68% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.
Compared with Astera Labs's other open jobs.
The team: ASIC Engineering HIRES STEADILY
This role is one of 52 open in ASIC Engineering. 14 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (35 of 52), Embedded Systems (21 of 52), Verilog (21 of 52), Perl (14 of 52), C (9 of 52), C++ (8 of 52), FPGA (5 of 52)
OTHER ROLES ON THIS TEAM
- Principal Digital Design Engineer posted Oct 14
- Principal Physical Design Engineer posted Oct 12
- Principal Physical Design CAD Engineer posted Oct 11
- Principal Digital Design Engineer posted Oct 5
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Senior System Validation Engineer posted Sep 16
- Digital Design Manager posted Sep 15
- Principal Digital Design Engineer posted Sep 14
- Manager Design Verification posted Sep 14
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Senior ATE Test Engineer posted Aug 31
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Physical Design Engineer, Methodology posted Jul 22
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- Soc Design Verification Director posted Jun 24
- Principal DFT Engineer posted Jun 8
- Staff DFT Engineer posted Jun 8
- Staff Physical Design Engineer - SoC EMIR Engineer posted Jun 7
- Physical Design Student posted Jun 2
- Staff/ Principal Design Verification Engineer posted Jun 1
- Senior Design Verification Engineer posted Jun 1
- Principal Physical Design Engineer, STA posted May 20
- Principal Product Engineer posted Apr 1
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- Principal ATE Test Engineer posted Dec 19
- Technical Chief of Staff for ASIC Engineering posted Nov 20
- Principal Emulation Engineer posted Sep 9
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
Salary context
16 other open postings titled Firmware Engineer state a salary: median USD 145,000 to USD 195,000 a year.
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