CPU Low Power RTL Design Engineer
- Salary
- $124,300 - $186,500
- Level
- Mid
- Work type
- On-site · Santa Clara
Not stated in the posting: visa.
Open. First seen 28 October 2026.
About the role
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. In this role, you will work with chip architects to…
What this role asks for
In most of Qualcomm's ads
Python
Named in most of its open postings, whatever the role.
Compared with Qualcomm's other open jobs.
The team: CPU Engineering
This role is one of 42 open in CPU Engineering. 23 were posted in the last 30 days, including 2 lead roles: the team is hiring the people who run it too.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (26 of 42), Perl (18 of 42), Verilog (14 of 42), C++ (12 of 42), C (11 of 42), VHDL (8 of 42), Embedded Systems (6 of 42)
OTHER ROLES ON THIS TEAM
- CPU Physical Electrical Analysis Engineer posted Oct 27
- Senior Software Engineer, Core AI Software - Haifa posted Oct 22
- CPU SRAM Design Engineer, Senior - Cork, Ireland posted Oct 15
- CPU Performance Architect/Modelling , Senior/Staff - Cork, Ireland posted Oct 14
- Principal CPU PPA Pathfinding Engineer posted Oct 13
- CPU Verification Engineer (Multiple Locations) posted Oct 13
- RTL Verification Engineer - Haifa posted Oct 13
- CPU Architect and Design - MMU & Security - Hod HaSharon posted Oct 12
- CPU Micro-architect/RTL Designer (Multiple Locations), Italy posted Oct 8
- CPU Verification Engineer posted Oct 8
- DV CAD Engineer posted Oct 7
- CPU SRAM Design Engineer posted Oct 7
- CPU Post-Silicon Performance Engineer posted Oct 7
- CPU Physical Design CAD Engineer (Sr Staff) posted Oct 6
- CPU Server Physical Design Methodology, Infrastructure and Automation Engineer posted Oct 6
- Software Engineer — RISC-V Random Test Generator posted Oct 2
- Senior Software Engineer — RISC-V Instruction Set Simulator (Simulator Engineer) posted Oct 2
- CPU Verification Engineer (RISC-V) posted Oct 2
- CPU Micro-Architecture and RTL Design Engineer (RISC-V) posted Oct 2
- CPU STA CAD Engineer posted Oct 2
- CPU SRAM Design Engineer - Sr Staff / Principal posted Oct 2
- CPU Server Physical Design Engineer, Santa Clara posted Oct 1
- CPU Verification Engineer, Director posted Sep 24
- CPU Security Architect posted Sep 23
- RISC-V Security Architect posted Sep 23
- CPU RTL/AI Micro-Architect - AI Development posted Sep 18
- CPU Micro-architect/RTL Designer posted Sep 18
- Senior Full Stack Software Engineer – CAD Infrastructure Team posted Sep 17
- CPU Architecture Performance Engineer (Multiple Levels) posted Sep 17
- CPU Synthesis CAD Engineer posted Sep 17
- CPU Integration CAD Engineer posted Sep 17
- CPU Post-Silicon Validation Engineer - Multiple Levels posted Sep 17
- CPU Physical Design Engineer posted Sep 17
- Server Product Architect (RISC-V) – Sr. Director posted Sep 17
- CPU Physical Design Timing Engineer (Austin, TX) posted Sep 17
- Principal CPU Power Modeling Engineer (San Diego, CA) posted Sep 17
- CPU Integration & 3DIC CAD Engineer posted Sep 17
- CPU Physical Design Engineer (Austin) posted Sep 17
- Server Postsilicon Project Engineer posted Sep 17
- CPU Performance Modeling Engineer (RISC-V) posted Sep 17
- CPU SRAM Design & Layout Engineer posted Sep 9
From the team and dates on Qualcomm's own job board.
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