ASIC Architect - Hod Hasharon

The team: CPU Engineering

This role is one of 73 open in CPU Engineering. 21 were posted in the last 30 days, including 3 lead roles: the team is hiring the people who run it too.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Python (41 of 73), Perl (30 of 73), Verilog (25 of 73), C++ (18 of 73), C (16 of 73), VHDL (15 of 73), Embedded Systems (14 of 73)

OTHER ROLES ON THIS TEAM

• CPU Server Physical Design Engineer posted Oct 29
• CPU Physical Electrical Analysis Engineer posted Oct 27
• CPU Design - Sr Engineer posted Oct 27
• CPU Design -Sr Engineer posted Oct 27
• CPU Design - Sr Engineer posted Oct 27
• CPU Low Power RTL Design Engineer posted Oct 22
• Senior Software Engineer, Core AI Software - Haifa posted Oct 22
• CPU SRAM Design Engineer, Senior - Cork, Ireland posted Oct 15
• CPU Performance Architect/Modelling , Senior/Staff - Cork, Ireland posted Oct 14
• Principal CPU PPA Pathfinding Engineer posted Oct 13
• CPU Verification Engineer (Multiple Locations) posted Oct 13
• RTL Verification Engineer - Haifa posted Oct 13
• CPU Architect and Design - MMU & Security - Hod HaSharon posted Oct 12
• CPU Micro-architect/RTL Designer (Multiple Locations), Italy posted Oct 8
• CPU Verification Engineer posted Oct 8
• DV CAD Engineer posted Oct 7
• CPU SRAM Design Engineer posted Oct 7
• CPU Post-Silicon Performance Engineer posted Oct 7
• CPU Physical Design CAD Engineer (Sr Staff) posted Oct 6
• CPU Server Physical Design Methodology, Infrastructure and Automation Engineer posted Oct 6
• Software Engineer — RISC-V Random Test Generator posted Oct 2
• Senior Software Engineer — RISC-V Instruction Set Simulator (Simulator Engineer) posted Oct 2
• CPU Verification Engineer (RISC-V) posted Oct 2
• CPU Micro-Architecture and RTL Design Engineer (RISC-V) posted Oct 2
• CPU STA CAD Engineer posted Oct 2
• CPU SRAM Design Engineer - Sr Staff / Principal posted Oct 2
• CPU Server Physical Design Engineer, Santa Clara posted Oct 1
• Server Power Management Sr. Staff Architect posted Sep 30
• Server SoC System Architect posted Sep 30
• CPU Server FV/CLP/STA engineer posted Sep 28
• CPU Verification Engineer, Director posted Sep 24
• CPU RTL Design Engineer (Senior/Staff) - Cambridge, UK posted Sep 23
• CPU Security Architect posted Sep 23
• RISC-V Security Architect posted Sep 23
• CPU RTL Methodology Engineer posted Sep 23
• CPU Design Verification Engineer (Senior level) - Cambridge, UK posted Sep 23
• CPU Physical Design Engineer, San Diego posted Sep 23
• Senior Staff RTL Design Engineer - Haifa or Hod HaSharon posted Sep 22
• CPU Server Floorplan and Integration Engineer posted Sep 22
• CPU Server Physical Design Timing Engineer posted Sep 22
• CPU Server Physical Design Clock Engineer posted Sep 22
• FPGA Engineer - Hod HaSharon posted Sep 22
• Principal CPU Physical Design Engineer (San Diego, CA) posted Sep 22
• CPU RTL/AI Micro-Architect - AI Development posted Sep 18
• CPU Micro-architect/RTL Designer posted Sep 18
• CPU Micro-architect/RTL Designer (Multiple Locations) posted Sep 17
• Senior CPU Performance Verification Engineer posted Sep 17
• Senior CPU Engineer posted Sep 17
• Server Project Engineer posted Sep 17
• CPU Synthesis CAD Engineer posted Sep 17
• CPU Integration CAD Engineer posted Sep 17
• CPU Post-Silicon Validation Engineer - Multiple Levels posted Sep 17
• CPU Physical Design Engineer posted Sep 17
• Server Product Architect (RISC-V) – Sr. Director posted Sep 17
• CPU Power and Thermal Management Architect posted Sep 17
• Senior Full Stack Software Engineer – CAD Infrastructure Team posted Sep 17
• CPU Integration & 3DIC CAD Engineer posted Sep 17
• CPU Physical Design Engineer (Austin) posted Sep 17
• CPU Server Physical Design Clock Engineer posted Sep 17
• CPU Performance Modeling Engineer (RISC-V) posted Sep 17
• CPU Architecture Performance Engineer (Multiple Levels) posted Sep 17
• CPU Formal Verification Engineer posted Sep 17
• CPU RTL Power Engineer posted Sep 17
• Lead Server Product Architect- Sr Director posted Sep 17
• CPU DFT Engineer posted Sep 17
• CPU System and Compute Die Architect posted Sep 17
• CPU Architecture Performance Engineer (RISC V) posted Sep 17
• CPU Physical Design Timing Engineer (Austin, TX) posted Sep 17
• Principal CPU Power Modeling Engineer (San Diego, CA) posted Sep 17
• CPU Emulation Engineer posted Sep 17
• CPU Systems RTL Engineer posted Sep 17
• CPU SRAM Design & Layout Engineer posted Sep 9

From the team and dates on Qualcomm's own job board.