Astera Labs

Technical Lead Digital Design Engineer

San Jose, California, United States
Salary
$160,000
Level
Lead

Not stated in the posting: work type, visa.

Open. First seen 2 November 2026.

About the role

Astera Labs's standard text

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Overview
Join our team as Technical Lead Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment.

Key Responsibilities

  • Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
  • Collaborate with verification teams to review test plans and debug issues.
  • Support efforts to achieve timing closure and implement Design-for-Test (DFT) features.
  • Scripting and automation for ASIC methodology improvement.
  • Accountable for quality and overall design success with the support of senior engineers.

Required Qualifications
Education & Experience:

  • Bachelor’s degree in electrical engineering or equivalent
  • 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets

Digital Design Expertise:

  • Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
  • Track record of delivering high-quality digital designs from definition to production.
  • Experience in high-speed design in advanced technology nodes.
  • Understanding of functional and formal verification at block and chip level.
  • Understanding of clocking, CDC and RDC and static-timing analysis

Protocols & Integration:

  • Proficient with high-speed protocols such as PCIe, Ethernet, DDR, or similar
  • Experience with IP development and integration

Tools & Methodologies:

  • Expertise in design methodology, CAD automation or design infrastructure.
  • Proven SystemVerilog and Python expertise in a production environment
  • Familiarity with Synopsys and/or Cadence digital design flows
  • Basic understanding of UVM-based verification methodologies

Professional Attributes:

  • Strong eagerness to learn and grow with the ability to balance multiple priorities in a dynamic environment
  • Good communication and collaboration skills; comfortable working cross-functionally with global teams
  • Self-directed learner who adapts quickly to changing requirements
  • Customer-focused mindset with the ability to prioritize and work independently to deliver high-quality designs.

Preferred Qualifications

  • Experience with embedded firmware development or standard embedded processor subsystems (RISC-V, Arm, etc.) is a plus
  • Knowledge of design-for-test (DFT) in a production environment.

Base salary range is $160,000 USD-$200,000 USD,and will be determined based on the candidate's capabilities and employees in similar positions.

Astera Labs's standard text

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

What this role asks for

In most of Astera Labs's ads

Python

Named in most of its open postings, whatever the role.

72% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.

Compared with Astera Labs's other open jobs.

The team: ASIC Engineering HIRES STEADILY

This role is one of 53 open in ASIC Engineering. 15 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.

WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS

Python (35 of 53), Embedded Systems (26 of 53), Verilog (23 of 53), Perl (17 of 53), C (7 of 53), C++ (6 of 53), FPGA (4 of 53)

OTHER ROLES ON THIS TEAM

From the team and dates on Astera Labs's own job board.

Similar jobs

More jobs like this

Is this your posting? Email info@careerholo.com to have it removed.