Lead Verification Engineer
- Salary
- $160,000 - $200,000
- Level
- Lead
Not stated in the posting: work type, visa.
Open. First seen 3 November 2026.
About the role
Astera Labs's standard text
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
As a Technical Lead on Verification at Astera Labs, you will be responsible for verifying the firmware and microcontroller subsystems for Astera Labs’ SoC and system products. In this role, you will play a key part in ensuring the quality and reliability of firmware by using both white-box and black-box testing methodologies. You will work closely with the firmware development team to build and execute test cases for specific components, identify bugs, and verify the overall implementation.
This role will focus on validating firmware for high-speed interfaces in data center, server, and networking applications.
Key Responsibilities
- Develop and execute test plans for firmware verification using white-box testing methodologies at the component level (e.g., PCIe, UART, SPI).
- Review code, identify bugs, and thoroughly test various firmware levels, including PHY, PCIe, and security features.
- Collaborate with the development team to ensure proper verification of hardware-software (HW-SW) interfaces on complex SoCs.
- Create automated test scripts using Python and manage test environments to ensure efficiency and accuracy in testing.
- Work with system-level validation and QA teams to ensure comprehensive testing of the entire product lifecycle.
Basic Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science (Master's preferred).
- +10 years of experience in firmware verification or development for SoC/silicon products.
- Proficiency in C and Python programming with experience in developing component-level test cases for firmware verification.
- Strong understanding of white-box testing methodologies, with experience in testing lower-level firmware components.
- Hands-on experience with server, storage, and/or networking equipment (e.g., PCIe/Ethernet Switches).
- Familiarity with high-speed interfaces and IP blocks such as PCIe Controllers, DDR Controllers, NVMe, AMBA/AHB interfaces, and on-chip memory.
- Experience working in software/firmware build environments (gcc/Make, GitHub) and test automation tools like Python.
Preferred Qualifications
- Experience developing or testing embedded firmware for high-speed interface products (e.g., PCIe, Ethernet).
- Familiarity with industry standards such as NIST, Open Compute Project, and DMTF.
- Knowledge of secure software, including cryptography, authentication, and common software vulnerabilities.
Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
Astera Labs's standard text
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
What this role asks for
Particular to this role
GitHub · Test Automation
Rare in Astera Labs's other 158 open postings.
In most of Astera Labs's ads
Python
Named in most of its open postings, whatever the role.
72% of this description is written for the role. The rest is Astera Labs's standard text, folded away below.
Compared with Astera Labs's other open jobs.
The team: ASIC Engineering HIRES STEADILY
This role is one of 55 open in ASIC Engineering. 18 were posted in the last 30 days and the oldest in August: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (36 of 55), Embedded Systems (26 of 55), Verilog (24 of 55), Perl (17 of 55), C (8 of 55), C++ (6 of 55), FPGA (4 of 55)
OTHER ROLES ON THIS TEAM
- Tech Lead, Asic Design posted Nov 4
- Tech Lead, Asic DV posted Nov 4
- Technical Lead Digital Design Engineer posted Nov 2
- Principal Digital Design Engineer posted Nov 2
- Principal Physical Design CAD Engineer posted Nov 1
- Staff / Principal ASIC Design Engineer posted Nov 1
- Physical Design Team Lead posted Nov 1
- Senior Design Verification Engineer posted Oct 27
- Principal Verification Engineer posted Oct 26
- Physical Design Team Lead posted Oct 25
- Physical Design Engineering Director posted Oct 24
- Principal Physical Design Engineer posted Oct 22
- Firmware Engineer posted Oct 20
- Principal Digital Design Engineer posted Oct 14
- Principal Physical Design Engineer posted Oct 12
- Principal Physical Design CAD Engineer posted Oct 11
- Principal Digital Design Engineer posted Oct 5
- Tech Lead, Digital Design Engineer posted Sep 30
- Principal Logic Design Engineer posted Sep 30
- Principal Verification Engineer posted Sep 29
- Tech Lead, Digital Design Engineer posted Sep 28
- Senior Design Verification Engineer posted Sep 28
- Tech Lead Engineer, Design Verification posted Sep 28
- Silicon Design Architect posted Sep 22
- DFT Engineer posted Sep 21
- Senior Manager, Digital Design posted Sep 17
- Principal Logic Design Engineer - UALink IP/Subsystem posted Sep 17
- Lead Logic Design Engineer posted Sep 17
- Senior System Validation Engineer posted Sep 16
- Digital Design Manager posted Sep 15
- Senior Design Verification Engineer posted Sep 11
- Senior STA Engineer posted Sep 11
- Senior Digital Design Engineer posted Sep 10
- Lead Logic Design Engineer posted Sep 10
- Principal Emulation Engineer posted Sep 9
- Principal Design Verification Engineer posted Aug 27
- System Validation Engineer posted Aug 17
- Post-Silicon Validation Engineer posted Aug 17
- Distinguished ASIC Design Engineer posted Aug 2
- Senior Principal ASIC Design Engineer posted Aug 2
- Principal Emulation Engineer posted Jul 16
- Staff / Principal ASIC Design Engineer posted Jul 16
- Technical Lead Physical Design Engineer posted Jul 1
- SoC Design Director posted Jun 29
- Soc Design Verification Director posted Jun 24
- Principal Architect posted Jun 9
- Physical Design Student posted Jun 2
- Product Technical Chip Lead, Senior Director posted Apr 9
- Senior Principal Digital Design Engineer posted Mar 12
- IP Design Verification Director posted Mar 5
- STA Physical Design Engineer, Senior Principal posted Feb 24
- Expert IC Package Design Lead posted Feb 22
- Lead HVM Product Engineer posted Aug 29
- Senior SoC Verification/Validation Engineer posted Aug 20
From the team and dates on Astera Labs's own job board.
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