IC Package FEA Engineer
- Level
- Senior
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
ABOUT LUMILENS
Lumilens's standard text
At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing - faster, cooler, and massively more efficient.
We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry. At Lumilens, we’re developing high-speed photonics products purpose-built to power the future of AI infrastructure and high-performance computing.
This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in scaling optical systems. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.
Lumilens's standard text
If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.
POSITION OVERVIEW
At Lumilens, we are redefining the optical layer that powers tomorrow’s AI and high‑performance computing. We are seeking an experienced IC Package Mechanical FEA Engineer to help drive the next generation of high‑performance packaging solutions for advanced ASICs.
In this role, you will join a globally distributed R&D organization developing mechanical designs that enable cutting‑edge systems for AI, networking, HPC, and 5G infrastructure. You will work hands‑on with emerging packaging and photonic‑integration technologies, including co‑packaged fiber‑optic transceivers, novel optical connectors, and complex chip‑stacking approaches such as 3DIC, hybrid copper bonding, and heterogeneous integration.
You will design, model, and optimize advanced multi‑chip‑module (MCM) architectures and mainstream flip‑chip BGA (FCBGA) packages to support Lumilens’ high‑speed photonic engines. Collaboration is central to this role: you will partner closely with R&D, manufacturing, and reliability teams to influence ASIC mechanical design from the earliest stages. Your engineering decisions will directly impact warpage, stress, reliability, cost, and overall thermal and electrical performance, ultimately shaping the photonics infrastructure that fuels future AI supercomputing.
Requirements:
- Bachelor’s in Mechanical Engineering (or related field) with 12+ years FEA experience, Master’s with 10+, or PhD with 7+.
- Deep expertise in advanced packaging technologies, including flip‑chip, FOWLP, 2.5D/3D integration, chiplet architectures, and TSVs.
- Strong understanding of materials behavior across polymers, metals, ceramics, and their thermo‑mechanical interactions.
- Familiarity with semiconductor packaging processes such as die attach, underfill, molding, bumping, and reflow.
- Proficiency with FEA tools, including Ansys Classic/Mechanical and Abaqus.
- Ability to interpret and correlate complex simulation results using first‑principles mechanical engineering concepts.
- Demonstrated experience calibrating models with empirical data, including hands‑on mechanical testing and metrology.
- Proven capability in developing and running lab‑level experiments to validate simulations and identify root causes.
- Strong judgment in balancing manufacturing constraints, reliability requirements, and performance needs.
- Excellent self‑management, organizational discipline, and ability to thrive in a fast‑moving environment.
- Comfortable collaborating with global, cross‑functional engineering teams and external vendors.
- Strong presentation, communication, and technical documentation skills.
Responsibilities:
- Perform FEA simulations to evaluate stress, strain, warpage, delamination, thermal cycling, and reliability risks across advanced package architectures (flip‑chip, fan‑out, 2.5D/3D IC, chiplet‑based, TSVs).
- Define simulation requirements, analyse results, and deliver actionable design and process recommendations.
- Support technology road mapping by assessing new materials, interconnect structures, and process flows from a thermo‑mechanical reliability perspective.
- Lead DOE studies and sensitivity analyses to identify key reliability and performance drivers.
- Collaborate with cross‑functional teams (design, photonics, manufacturing, reliability, vendors) to ensure robust, scalable package architectures.
*All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
What this role asks for
Particular to this role
ANSYS · FEA
Rare in Lumilens's other 121 open postings.
90% of this description is written for the role. The rest is Lumilens's standard text, folded away below.
Read against Lumilens's other open postings on this site.
The team: Engineering HIRES STEADILY
This role is one of 41 open in Engineering. 3 were posted in the last 30 days and the oldest in September: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (18 of 41), Embedded Systems (9 of 41), C++ (7 of 41), Test Automation (7 of 41), C (5 of 41), Linux (5 of 41), Perl (4 of 41)
OTHER ROLES ON THIS TEAM
- Analog and Mixed Signal Layout Engineer posted Oct 7
- Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon posted Sep 24
- IC Layout Engineer – Optical Engine Silicon posted Sep 24
- Senior / Staff ATE Test Engineer – Optical Transceiver Silicon posted Sep 16
- ATE Test Engineer – Optical Transceiver Silicon posted Sep 16
- Active Alignment & NPI Process Development Engineer posted Sep 9
- Senior/ Staff NPI Wafer Bumping/Fan-Out Process Engineer posted Sep 7
- DSP Engineer posted Aug 31
- Silicon Photonic Engineer posted Aug 28
- Silicon Test Engineer posted Aug 5
- Senior Director, Hardware Engineering posted Jul 31
- Senior Silicon Photonics Test Engineer (NPI) posted Jul 29
- Staff Silicon Photonics Test Engineer posted Jul 23
- Senior Silicon Photonics Test Engineer posted Jul 23
- Senior Manager, Silicon Photonics Testing and Packaging posted Jul 20
- Senior Silicon Photonics Engineer posted Jul 15
- Sr. Physical Design Engineer posted Jul 10
- IC Design Verification Engineer posted Jul 6
- IC/RTL Design Engineer posted Jul 6
- Principal Engineer Silicon Photonics posted Jun 25
- Modelling Lead (SystemC / Virtual-Platform Architect) posted Jun 24
- Modelling Lead (SystemC / Virtual-Platform Architect) posted Jun 24
- RTL Design Lead/IC Front-End Architect/Datapath Lead posted Jun 24
- RTL Design Lead/IC Front-End Architect/Datapath Lead posted Jun 24
- Optical Systems Engineer Lead posted Jun 18
- Power Integrity Engineer-Silicon posted Jun 17
- Hardware Test Engineer posted Jun 17
- Principal Mechanical Engineer posted Jun 12
- Silicon Test Engineer posted May 29
- Silicon Photonic Engineer (CPO) posted May 20
- Senior Technical Program Manager (Silicon) posted May 7
- Senior Staff Software Engineer (MES & Distribution Systems) posted Apr 17
- Director of Silicon Test Engineering posted Mar 23
- Optical Test Engineer posted Mar 22
- Advanced Package Technology Principal Engineer posted Mar 22
- Senior Signal Integrity Engineer posted Feb 4
- Signal Integrity Engineer-1.6 OSFP Board Design posted Feb 4
- Senior/Principal Analog & Mixed Signal Design Engineers posted Dec 29
- Senior Software Test Automation Engineer posted Sep 25
- Systems Applications Engineer - Optical posted Sep 1
From the team and dates on Lumilens's own job board.
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