RTL Design Lead/IC Front-End Architect/Datapath Lead
- Level
- Lead
Not stated in the posting: salary, work type, visa.
Open. First seen 2 October 2026.
About the role
About Lumilens
Lumilens's standard text
At Lumilens we are building the critical photonics infrastructure that powers tomorrow’s AI supercomputing. From chip-to-chip optical interconnects to scalable photonic engines, Lumilens is unlocking a new era of computing faster, cooler, and massively more efficient.
We’re a well-funded startup backed by Mayfield and led by veterans who’ve built and scaled some of the most transformative technologies in the industry.
This isn’t incremental innovation, it’s a ground-floor opportunity to rethink the optical layer from the silicon up. The market is moving fast, and we’re moving faster. You’ll work alongside a team of world-class engineers solving some of the hardest challenges in optics, systems, and scale. Every line of code, every design decision, every breakthrough you help deliver will shape the infrastructure of tomorrow.
Lumilens's standard text
If you're looking for mission, momentum, and the chance to make an outsized impact, jump on the rocket ship. We’re just getting started.
About the Role
You own verification end to end for a first-of-its-kind chiplet. As a founding hire you define the methodology before there's RTL to verify — this role is on the critical path, and getting the coverage strategy and regression infrastructure right early is the single biggest schedule lever we have.
About the role. You define the digital front-end micro-architecture — the spec the design team implements — and personally own the high-speed datapath that moves data between UCIe and the optical front end. This is the architectural center of the chip: the datapath, the UCIe streaming interface, in-house IP, and the interface to the optical engine all converge in your blocks. As a founding hire you set the partitioning, interfaces, and coding/CDC standards the whole front end follows.
What you'll own
- Front-end micro-architecture and block partitioning; the architecture spec the RTL team builds to.
- Front-end design methodology and quality: RTL coding standards, lint, CDC/RDC signoff, and clean-RTL policy across the team.
- The high-speed datapath: per-lane alignment/deskew/mux, the UCIe streaming /RDI adapter, elastic FIFOs, and custom logic.
- Transport/link framing/mapping and the adaptation logic.
- Timing- and floorplan-aware micro-architecture: pipelining, retiming, and partitioning for physical closure at multi-hundred-Gbps (with the backend team).
- Clocking, reset, and low-power architecture — clock/reset domains, gating strategy, and UPF power intent.
- Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA) coverage that designers own before handoff to DV.
- Architectural DFT and debug provisioning — scan-friendly structure and on-die observability/controllability for a die you can't probe (with the DFT and DV leads).
- IP integration and interface/register conventions; parameterization for configurability across lane counts/configurations.
- Architectural trade-offs with the modelling lead (latency, buffering, datapath sampling/observability) and the DV lead (verifiability and debug).
- Lead, grow, and mentor the front-end design team as the group scales (datapath, interfaces, integration).
Required
- 10+ years digital design / micro-architecture, with lead ownership of a high-throughput datapath or SerDes-adjacent SoC.
- Experience designing the datapath of a network switch/NIC card or memory controller at a major XPU / fabric vendor (or a comparable high-throughput, high-reliability datapath).
- Solid understanding of scale-up vs. scale-out interconnect architectures and their bandwidth/latency trade-offs.
- Strong SystemVerilog RTL and timing-aware micro-architecture at multi-hundred-Gbps aggregate rates; CDC discipline.
- Working command of UCIe/PCIe/CXL datapath concepts and high-speed lane alignment/deskew.
- Proven ownership of front-end design methodology — lint/CDC/RDC signoff, clocking/reset architecture, and design-for-test and physical-closure collaboration.
- Track record translating system requirements into an implementable, verifiable architecture spec.
Preferred
- UCIe (or PCIe/CXL/CHI) interface architecture; die-to-die / chiplet experience.
- FEC/coding datapath familiarity (e.g., Reed-Solomon) and gray-code mapping.
- Optical transceiver, CPO, or linear-drive optics background; advanced-node (N5/N3/N2) design experience.
What We Offer
- Competitive salary commensurate with experience
- Comprehensive benefits package including health, dental, and vision
- Professional development opportunities and certification support
- Access to cutting-edge technology and cloud platforms
- Collaborative work environment with cross-functional teams
Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender identity, sexual orientation, veteran status, disability, or any other legally protected status.
What this role asks for
Particular to this role
Verilog
Rare in Lumilens's other 121 open postings.
91% of this description is written for the role. The rest is Lumilens's standard text, folded away below.
Read against Lumilens's other open postings on this site.
The team: Engineering HIRES STEADILY
This role is one of 41 open in Engineering. 3 were posted in the last 30 days and the oldest in September: a team that hires all year rather than one being built.
WHAT THE TEAM WORKS WITH, ACROSS ITS POSTINGS
Python (18 of 41), Embedded Systems (9 of 41), C++ (7 of 41), Test Automation (7 of 41), C (5 of 41), Linux (5 of 41), Perl (4 of 41)
OTHER ROLES ON THIS TEAM
- Analog and Mixed Signal Layout Engineer posted Oct 7
- Senior/Staff/Principal IC Layout Engineer – Optical Engine Silicon posted Sep 24
- IC Layout Engineer – Optical Engine Silicon posted Sep 24
- Senior / Staff ATE Test Engineer – Optical Transceiver Silicon posted Sep 16
- ATE Test Engineer – Optical Transceiver Silicon posted Sep 16
- Active Alignment & NPI Process Development Engineer posted Sep 9
- Senior/ Staff NPI Wafer Bumping/Fan-Out Process Engineer posted Sep 7
- DSP Engineer posted Aug 31
- Silicon Photonic Engineer posted Aug 28
- Silicon Test Engineer posted Aug 5
- Senior Director, Hardware Engineering posted Jul 31
- Senior Silicon Photonics Test Engineer (NPI) posted Jul 29
- Staff Silicon Photonics Test Engineer posted Jul 23
- Senior Silicon Photonics Test Engineer posted Jul 23
- Senior Manager, Silicon Photonics Testing and Packaging posted Jul 20
- Senior Silicon Photonics Engineer posted Jul 15
- Sr. Physical Design Engineer posted Jul 10
- IC Design Verification Engineer posted Jul 6
- IC/RTL Design Engineer posted Jul 6
- Principal Engineer Silicon Photonics posted Jun 25
- Modelling Lead (SystemC / Virtual-Platform Architect) posted Jun 24
- Modelling Lead (SystemC / Virtual-Platform Architect) posted Jun 24
- RTL Design Lead/IC Front-End Architect/Datapath Lead posted Jun 24
- Optical Systems Engineer Lead posted Jun 18
- Power Integrity Engineer-Silicon posted Jun 17
- Hardware Test Engineer posted Jun 17
- Principal Mechanical Engineer posted Jun 12
- Silicon Test Engineer posted May 29
- Silicon Photonic Engineer (CPO) posted May 20
- Senior Technical Program Manager (Silicon) posted May 7
- Senior Staff Software Engineer (MES & Distribution Systems) posted Apr 17
- Director of Silicon Test Engineering posted Mar 23
- Optical Test Engineer posted Mar 22
- Advanced Package Technology Principal Engineer posted Mar 22
- IC Package FEA Engineer posted Mar 22
- Senior Signal Integrity Engineer posted Feb 4
- Signal Integrity Engineer-1.6 OSFP Board Design posted Feb 4
- Senior/Principal Analog & Mixed Signal Design Engineers posted Dec 29
- Senior Software Test Automation Engineer posted Sep 25
- Systems Applications Engineer - Optical posted Sep 1
From the team and dates on Lumilens's own job board.
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